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1/130 STLC5466 november 1999 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. preliminary data 64 channel-multi hdlc with n x 64kb/s switching matrix associated n 64 tx hdlcs with broadcasting capability and/ or csma/cr function with automatic restart in case of tx frame abort n 64 rx hdlcs including address recognition n 16 command/indicate channels (4 or 6-bit primitive) n 16 monitor channels processed in accordance with gci or v* n 256 x 256 switching matrix without blocking and with time slot sequence integrity and loopback per bidirectional connection n dma controller for 64 tx channels and 64 rx channels n hdlcs and dma controller are capable of handling a mix of lapd,lapb, ss7, cas and proprietary signallings n external shared memory access between dma controller and micro processor n single memory shared between n x multi-hdlcs and single micro processor allows to handle n x 64 channels n bus arbitration n interface for various 8,16 or 32 bit microprocessors with fetch memory to accelerate the exchanges between microprocessor and shared memory n sdram controller allows to inter face up to 16 megabytes of synchronous dynamic ram n interrupt controller to store automatically events in shared memory n boundary scan for test facility n tqfp176 package 24 x 24 x 1.40 #ms-026bga n hcmos6; 0.35 micron; 3.3volts +/-5% n operating temperature: -40 to +85 /c description the STLC5466 is a subscriber line interface card controller for central office, central exchange, nt2 and pbx capable of handling: n 16 u interfaces or n 2 megabits line interface cards or n 16 slics (plain old telephone service) or n mixed analogue and digital interfaces (slics or u interfaces) or n 16 s interfaces n switching network with centralized processing. tqfp176 (plastic quad flat pack) ordering number: STLC5466
STLC5466 2/130 table of contents i pin information............................................................................................................... .6 i.1 pin connections ............................................................................................................. .6 i.2 pin description ................................................................. ............................................ ..7 i.3 pin definition...................................................................... ........................................ ....12 i.3.1 input pin definition...................................................................................................... ..........12 i.3.2 output pin definition .................................................................................................... ........12 i.3.3 input/output pin definition. ............................................................................................. .....12 ii block diagram ...............................................................................................................1 3 iii functional description .............................................................................................13 iii.1 the switching matrix n x 64 kbits/s........................................................................13 iii.1.1 function description .................................................................................................... .........13 iii.1.2 architecture of the matrix ............................................................................................. ........13 iii.1.3 connection function .................................................................................................... ........13 iii.1.4 loop back function ..................................................................................................... ........15 iii.1.5 delay through the matrix ............................................................................................... .......15 iii.1.5.1 variable delay mode .................................................................................................. ......15 iii.1.5.2 sequence integrity mode ............................................................................................... ...15 iii.1.6 connection memory ...................................................................................................... .......15 iii.1.6.1 description .......................................................................................................... .............15 iii.1.6.2 access to connection memory .........................................................................................15 iii.1.6.3 access to data memory................................................................................................. ...15 iii.1.7 switching at 32 kbit/s ................................................................................................. ..........15 iii.1.8 switching at 16 kbit/s ................................................................................................. ..........16 iii.2 hdlc controller.............................................................. ............................................1 6 iii.2.1 function description ................................................................................................... ..........16 iii.2.1.1 format of the hdlc frame .............................................................................................. 16 iii.2.1.2 composition of an hdlc frame.......................................................................................16 iii.2.1.3 description and functions of the hdlc bytes..................................................................16 iii.2.2 csma/cr capability ..................................................................................................... .......17 iii.2.3 time slot assigner memory .............................................................................................. ...17 iii.2.4 data storage structure .................................................................................................. .......18 iii.2.4.1 reception............................................................................................................. .............18 iii.2.4.2 transmission.......................................................................................................... ...........18 iii.2.4.3 frame relay ........................................................................................................... ..........18 iii.2.5 transparent modes ...................................................................................................... ........18 iii.2.6 command of the hdlc channels ........................................................................................19 iii.2.6.1 reception control ..................................................................................................... ........19 iii.2.6.2 transmission control .................................................................................................. ......19 iii.3 c/i and monitor.................................................................. ......................................... ...19 iii.3.1 function description ................................................................................................... .........19 iii.3.2 gci and v* protocol .................................................................................................... .........19
3/130 STLC5466 iii.3.3 structure of the treatment ............................................................................................. ......20 iii.3.4 ci and monitor channel configuration..................................................................................20 iii.3.5 ci and monitor transmission/reception command .............................................................20 iii.4 scrambler and descrambler...................................... ............................................20 iii.5 connection between isdn channels and gci channels..............................20 iii.6 microprocessor interface......................................... ............................................21 iii.6.1 description ............................................................................................................ ...............21 iii.6.2 buffer ................................................................................................................. ..................21 iii.6.2.1 write fifo ............................................................................................................ ............21 iii.6.2.2 read fetch memory ..................................................................................................... ....23 iii.6.2.3 definition of the interface for the different microprocessors..............................................23 iii.7 memory interface ........................................................... ............................................23 iii.7.1 function description ................................................................................................... .........23 iii.7.2 choice of memory versus microprocessor and capacity required ........................................23 iii.7.3 memory cycle ............................................................................................................ ...........23 iii.7.4 memories composed of different circuits ..............................................................................23 iii.7.4.1 memory obtained with 1m x16 sdram circuit..................................................................23 iii.7.4.2 memory obtained with 2m x 8 sdram circuit...................................................................23 iii.7.4.3 memory obtained with 8m x 8 sdram circuit...................................................................23 iii.7.4.4 memory obtained with 4m x 16 sdram circuit.................................................................24 iii.8 bus arbitration ................................................................ ........................................... .24 iii.9 clocks .................................................................................. .................................. ..........24 iii.9.1 clock distribution selection and supervision .......................................................................24 iii.9.2 vcxo frequency synchronization .......................................................................................24 iii.10 interrupt controller................................................... ............................................25 iii.10.1 description ........................................................................................................... ................25 iii.10.2 operating interrupts (int0 pin)........................................................................................ .....25 iii.10.3 time base interrupts (int1 pin) ........................................................................................ ...25 iii.10.4 emergency interrupts (wdo pin) ......................................................................................... 25 iii.10.5 interrupt queues ...................................................................................................... ............25 iii.11 watchdog............................................................................ ..................................... .......25 iii.12 reset ..................................................................................... ............................... .............25 iii.13 boundary scan.................................................................. .......................................... ..26 iv dc specifications..........................................................................................................27 v list of registers ..........................................................................................................29 vi internal registers ......................................................................................................31 vi.1 identification and dynamic command register... idcr (00)h .........................31 vi.2 general configuration register 1 .......................... gcr1 (02)h........................31 vi.3 input multiplex configuration register 0............ imcr0 (04)h.......................33
STLC5466 4/130 vi.4 input multiplex configuration register 1 ........... imcr1 (06)h.......................34 vi.5 output multiplex configuration register 0........ omcr0 (08)h.....................34 vi.6 output multiplex configuration register 1........ omcr1 (0a)h ....................34 vi.7 switching matrix configuration register ........... smcr (0c)h.......................35 vi.8 connection memory data register ......................... cmdr (0e)h.......................37 vi.9 connection memory address register ................. cmar (10)h .......................41 vi.10 sequence fault counter register ......................... sfcr (12)h ........................45 vi.11 time slot assigner address register 1.................. taar1 (14)h ......................45 vi.12 time slot assigner data register 1 ......................... tadr1 (16)h ......................45 vi.13 hdlc transmit command register 1 ......................... htcr1 (18)h......................46 vi.14 hdlc receive command register 1 ............................ hrcr1 (1a)h .....................48 vi.15 address field recognition address register 1 . afrar1 (1c)h ...................50 vi.16 address field recognition data register 1 ......... afrdr1 (1e)h ...................50 vi.17 fill character register 1 ............................................ fcr1 (20)h ........................51 vi.18 gci channels definition register 0 ......................... gcir0 (22)h.......................51 vi.19 gci channels definition register 1 .......................... gcir1 (24)h.......................51 vi.20 gci channels definition register 2 .......................... gcir2 (26)h.......................52 vi.21 gci channels definition register 3 .......................... gcir3 (28)h.......................52 vi.22 transmit command / indicate register .................. tcir (2a)h .........................52 vi.23 transmit monitor address register....................... tmar (2c)h .......................53 vi.24 transmit monitor data register .............................. tmdr (2e)h .......................54 vi.25 transmit monitor interrupt register.................... tmir (30)h .........................55 vi.26 memory interface configuration register......... micr (32)h.........................55 vi.27 initiate block address register 1 ........................... ibar1 (34)h .......................56 vi.28 interrupt queue size register ................................. iqsr (36)h .........................56 vi.29 interrupt register ........................................................ ir (38)h ..............................57 vi.30 interrupt mask register.............................................. imr (3a)h...........................58 vi.31 timer register 1 ............................................................... timr1 (3c)h ......................59 vi.32 test register .................................................................... tr (3e)h.............................59 vi.33 general configuration register 2 .......................... gcr2 (42)h........................60 vi.34 split fetch memory register ..................................... sfmr (4e)h .......................61 vi.35 time slot assigner address register 2.................. taar2 (54)h ......................62 vi.36 time slot assigner data register 2 ......................... tadr2 (56)h ......................62 vi.37 hdlc transmit command register 2 ........................ htcr2 (58)h......................63
5/130 STLC5466 vi.38 hdlc receive command register 2 ........................... hrcr2 (5a)h .....................65 vi.39 address field recognition address register 2 afrar2 (5c)h ...................67 vi.40 address field recognition data register 2 ......... afrdr2 (5e)h ...................67 vi.41 fill character register 2 ........................................... fcr2 (60)h ........................68 vi.42 sdram mode register..................................................... sdramr (72)h ..................68 vi.43 initiate block address register 2 ........................... ibar2 (74)h .......................69 vi.44 timer register 2 ............................................................... timr2 (7c)h ......................70 vii external registers.....................................................................................................71 vii.1 initialization block in external memory (iba1 and iba2) 71 vii.2 receive descriptor......................................................... 72 vii.2.1 bits written by the microprocessor only ...............................................................................7 2 vii.2.2 bits written by the rx dmac only ....................................................................................... .72 vii.2.3 receive buffer ......................................................................................................... ............73 vii.3 transmit descriptor ...................................................... ............................................73 vii.3.1 bits written by the microprocessor only ...............................................................................7 3 vii.3.2 bits written by the tx dmac only ....................................................................................... .74 vii.3.3 transmit buffer ........................................................................................................ ............74 vii.4 receive & transmit hdlc frame interrupt ............ ............................................75 vii.5 receive command / indicate interrupt.................... ............................................76 vii.5.1 receive command / indicate interrupt when tsv = 0 .........................................................76 vii.5.2 receive command / indicate interrupt when tsv = 1 .........................................................77 vii.6 receive monitor interrupt.......................................... ............................................77 vii.6.1 receive monitor interrupt when tsv = 0 .............................................................................77 vii.6.2 receive monitor interrupt when tsv = 1 .............................................................................78 viii tqfp176 package mechanical data .......................................................................79 ix figures and timing........................................................................................................80
STLC5466 6/130 i - pin information i.1 - pin connections 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 n.c vdd14 ec2 nce3/adm13 cb2 nce2/adm12 udqm nce1 ldqm nce0 nras nwe tro tri vss7 vdd7 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 vss6 vdd6 a23 a22 a21 a20 a19 a18 a17 a16 vss13 n.c n.c vss15 nreset mclk sfs wdo cb1 ec1 vcxo in vcxo out dclk clocka clockb framea frameb vdd1 vss1 fs fscg fscv pss din0 din1 din2 din3 din4 din5 din6 din7 din8 vdd2 vss2 dout0 dout1 dout2 dout3 dout4 dout5 dout6 dout7 ndis/ncs2 ntrst vdd12 n.c n.c vss12 tms tdi tdo tck vdd3 vss3 ncs0 ncs1 int0 int1 size0/nlds/nlba size1/nbhe/nuds ndsack0/ndtack ndsack1/ready nas/ale r/w / nwr nds/nrd/clkout mod0 mod1 mod2 vdd4 vss4 a0/ad0 a1/ad1 a2/ad2 a3/ad3 a4/ad4 a5/ad5 a6/ad6 a7/ad7 a8/ad8 a9/ad9 vdd5 vss5 a10/ad10 a11/ad11 a12/ad12 a13/ad13 a14/ad14 a15/ad15 vdd13 n.c n.c vdd15 ntest vss11 vdd11 dm15 dm14 dm13 dm12 dm11 dm10 dm9 dm8 dm7 dm6 dm5 vss10 vdd10 dm4 dm3 dm2 dm1 dm0 din9 scanm ncas adm11 adm10 vss9 vdd9 adm9 adm8 adm7 adm6 adm5 adm4 adm3 adm2 adm1 adm0 vss8 vdd8 vss14 n.c nready 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 STLC5466
7/130 STLC5466 i.2 - pin description pin n symbol type function 30 power pins (all the power and ground pins must be connected) 16 v dd1 power dc supply 17 v ss1 ground dc ground 31 v dd2 power dc supply 32 v ss2 ground dc ground 51 v dd3 power dc supply 52 v ss3 ground dc ground 67 v dd4 power dc supply 68 v ss4 ground dc ground 79 v dd5 power dc supply 80 v ss5 ground dc ground 99 v dd6 power dc supply 100 v ss6 ground dc ground 117 v dd7 power dc supply 118 v ss7 ground dc ground 135 v dd8 power dc supply 136 v ss8 ground dc ground 147 v dd9 power dc supply 148 v ss9 ground dc ground 159 v dd10 power dc supply 160 v ss10 ground dc ground 172 v dd11 power dc supply 173 v ss11 ground dc ground 43 v dd12 power dc supply 46 v ss12 ground dc ground 87 v dd13 power dc supply 90 v ss13 ground dc ground 131 v dd14 power dc supply 134 v ss14 ground dc ground 175 v dd15 power dc supply 2 v ss15 ground dc ground clocks 4 mclk i3_ft master clock. this input can receive an external clock at 66, 50 or 33mhz. 5 sfs o3_ft superframe synchronisation. programmable signal from 250 microseconds to 15 seconds. type ft: five volts tolerant fnt: five volts not tolerant ttl i1_ft = input ttl i2_ft = i1_ft+pull up i3_ft = i1_ft+hysteresis i4_ft = i3_ft+pull up ttl i/o6 _ft = input ttl/ output ttl 6 ma i5_ft = i3_ft+pull down; ttl o3 _ft = output ttl 3 ma o3t_ft = o3_ft+tristate o6_ft = output ttl 6ma ttl o6d_ft = output ttl 6ma, open drain o6dt_ft = output ttl 6ma, open drain or tristate cmos i/o8_fnt = input ttl, /output cmos 8ma; o8t_fnt = output cmos 8ma i/o8_fnt = input ttl, /output cmos 8ma cmos o4_fnt = output cmos 4ma
STLC5466 8/130 9 vcxo in i3_ft vcxo input signal. this signal is compared to clock a(orb) selected inside the multi-hdlc . 10 vcxo out o3_ft vcxo error signal. this pin delivers the result of the comparison. 12 clocka i3_ft input clock a (4096khz or 8192khz) 13 clockb i3_ft input clock b (4096khz or 8192khz) 14 framea i3_ft clock a at 8khz 15 frameb i3_ft clock b at 8khz 11 dclk o6_ft data clock issued from input clock a (or b). this clock is delivered by the cir- cuit at 4096khz (or 2048khz). dout0/7 are transmitted on the rising edge of this signal. din0/7 are sampled on the falling edge of this signal. 19 fscg o6_ft frame synchronization for gci at 8khz. this clock is issued from frame a (or b). 20 fscv* o6_ft frame synchronization for v star at 8khz 18 fs i3_ft frame synchronization. this signal synchronizes din0/8 and dout0/7 and cb. 21 pss o3_ft programmable synchronization signal. pss is programmed by the ps bit of connection memory. time division multiplexes (tdm) 22 din0 i3_ft tdm0 data input 0 23 din1 i3_ft tdm1 data input 1 24 din2 i3_ft tdm2 data input 2 25 din3 i3_ft tdm3 data input 3 26 din4 i3_ft tdm4 data input 4 27 din5 i3_ft tdm5 data input 5 28 din6 i3_ft tdm6 data input 6 29 din7 i3_ft tdm7 data input 7 30 din8 i3_ft tdm8 data input 8, direct access to 1st 32 hdlc controller 153 din9 i3_ft tdm9 data input 9, direct access to 2nd 32 hdlc controller 33 dout0 o6dt_ft tdm0 data output 0 34 dout1 o6dt_ft tdm1 data output 1 35 dout2 o6dt_ft tdm2 data output 2 36 dout3 o6dt_ft tdm3 data output 3 37 dout4 o6dt_ft tdm4 data output 4 38 dout5 o6dt_ft tdm5 data output5 39 dout6 o6dt_ft tdm6 data output6 40 dout7 o6dt_ft tdm7 data output 7 pin n symbol type function type ft: five volts tolerant fnt: five volts not tolerant ttl i1_ft = input ttl i2_ft = i1_ft+pull up i3_ft = i1_ft+hysteresis i4_ft = i3_ft+pull up ttl i/o6 _ft = input ttl/ output ttl 6 ma i5_ft = i3_ft+pull down; ttl o3 _ft = output ttl 3 ma o3t_ft = o3_ft+tristate o6_ft = output ttl 6ma ttl o6d_ft = output ttl 6ma, open drain o6dt_ft = output ttl 6ma, open drain or tristate cmos i/o8_fnt = input ttl, /output cmos 8ma; o8t_fnt = output cmos 8ma i/o8_fnt = input ttl, /output cmos 8ma cmos o4_fnt = output cmos 4ma
9/130 STLC5466 41 ndis/ncs2 i3_ft if 386ex interface is not selected: dout 0/7 not disable. when this pin is at 0v, the data output 0/7 are at high impedance. wired at v dd if not used. if 386ex interface is selected: ncs2 (chip select 2) equivalent to ncs1. chip select 2: external memory is selected during chip select (ncs2=0), the output ready (pin 59) is low impedance and outside chip select (ncs2=1), the output ready is high impedance. 7 cb1 o6d_ft contention bus (csma/cr) for 1st 32 hdlc controller 8 ec1 i3_ft echo for 1st 32 hdlc controller. wired at v ss if not used. 128 cb2 o6d_ft contention bus (csma/cr) for 2nd 32 hdlc controller 130 ec2 i3_ft echo for 2nd 32 hdlc controller. wired at v ss if not used. boudary scan 42 ntrst i4_ft reset for boundary scan 47 tms i2_ft mode selection for boundary scan 48 tdi i2_ft input data for boundary scan 49 tdo o3t_ft output data for boundary scan 50 tck i4_ft clock for boundary scan microprocessor interface 64 mod0 i1_ft 1 1 0 0 1 1 0 0 65 mod1 i1_ft 1 1 0 0 0 0 1 1 66 mod2 i1_ft 01100110 80c188 80c186 68000 68020 st9 st10 m st10nm 386ex 3 nreset i3_ft circuit reset 53 ncs0 i3_ft chip select 0: internal registers are selected 54 ncs1 i3_ft chip select 1: external memory is selected during chip select (ncs1=0), the output ready (pin 59) is low impedance and outside chip select (ncs1=1), the output ready is high impedance. 55 int0 o3_ft interrupt generated by hdlc, rxc/i or rxmon. active high. 56 int1 o3_ft interrupt1.this pin goes to 5v when the selected clock a (or b) has disap- peared; 250 m s after reset this pin goes to 5v also if clock a is not present. 6 wdo o3_ft watch dog output.this pin goes to 5v during 250 m s when the microprocessor has not reset the watch dog during the programmable time. 57 size0/nlds/nlba i3_ft transfer size0 (68020)/lower data stobe/local bus access# when 386ex 58 size1/nbhe/nuds i3_ft transfer size1(68020)/bus high enable (intel) / upper data strobe (68000) 59 ndsack0/ ndtack/ nready o6t_ft/ o6t_ft/ o6d_ft data strobe, acknowledge and size0 (68020)/ data transfer acknowledge (68000 and st10)/ ready# (386ex) 60 ndsack1/ ready o6t_ft o6t_ft data strobe, acknowledge and size1 (68020)/ data transfer acknowledge (intel) 61 nas/ ale/nads i3_ft address strobe(motorola) / address latch enable(intel) / address status 386ex 62 r/w / nwr i3_ft read/write (motorola) / write(intel) pin n symbol type function type ft: five volts tolerant fnt: five volts not tolerant ttl i1_ft = input ttl i2_ft = i1_ft+pull up i3_ft = i1_ft+hysteresis i4_ft = i3_ft+pull up ttl i/o6 _ft = input ttl/ output ttl 6 ma i5_ft = i3_ft+pull down; ttl o3 _ft = output ttl 3 ma o3t_ft = o3_ft+tristate o6_ft = output ttl 6ma ttl o6d_ft = output ttl 6ma, open drain o6dt_ft = output ttl 6ma, open drain or tristate cmos i/o8_fnt = input ttl, /output cmos 8ma; o8t_fnt = output cmos 8ma i/o8_fnt = input ttl, /output cmos 8ma cmos o4_fnt = output cmos 4ma
STLC5466 10/130 63 nds/ nrd/clkout i3_ft data strobe (motorola) external resistor at vss if 68000/ read data (intel)/clkout if 386ex 69 a0/ad0 i/o6_ft address bit 0 (motorola) / address/data bit 0 (intel) 70 a1/ad1 i/o6_ft address bit 1 (motorola) / address/data bit 1 (intel) 71 a2/ad2 i/o6_ft address bit 2 (motorola) / address/data bit 2 (intel) 72 a3/ad3 i/o6_ft address bit 3 (motorola) / address/data bit 3 (intel) 73 a4/ad4 i/o6_ft address bit 4 (motorola) / address/data bit 4 (intel) 74 a5/ad5 i/o6_ft address bit 5 (motorola) / address/data bit 5 (intel) 75 a6/ad6 i/o6_ft address bit 6 (motorola) / address/data bit 6 (intel) 76 a7/ad7 i/o6_ft address bit 7 (motorola) / address/data bit 7 (intel) 77 a8/ad8 i/o6_ft address bit 8 (motorola) / address/data bit 8 (intel) 78 a9/ad9 i/o6_ft address bit 9 (motorola) / address/data bit 9 (intel) 81 a10/ad10 i/o6_ft address bit 10 (motorola) / address/data bit 10 (intel) 82 a11/ad11 i/o6_ft address bit 11 (motorola) / address/data bit 11 (intel) 83 a12/ad12 i/o6_ft address bit 12 (motorola) / address/data bit 12 (intel) 84 a13/ad13 i/o6_ft address bit 13 (motorola) / address/data bit 13 (intel) 85 a14/ad14 i/o6_ft address bit14 (motorola) / address/data bit 14 (intel) 86 a15/ad15 i/o6_ft address bit15 (motorola) / address/data bit 15 (intel) 91 a16 i1_ft address bit16 from m p 92 a17 i1_ft address bit17 from m p 93 a18 i1_ft address bit18 from m p 94 a19 i1_ft address bit19 from m p 95 a20 i1_ft address bit 20 from m p 96 a21 i1_ft address bit 21 from m p 97 a22 i1_ft address bit 22 from m p 98 a23 i1_ft address bit 23 from m p 101 do i/o6_ft data bit 0 for m p if not multiplexed (see note 1). 102 d1 i/o6_ft data bit 1 for m p if not multiplexed 103 d2 i/o6_ft data bit 2 for m p if not multiplexed 104 d3 i/o6_ft data bit 3 for m p if not multiplexed 105 d4 i/o6_ft data bit 4 for m p if not multiplexed 106 d5 i/o6_ft data bit 5 for m p if not multiplexed 107 d6 i/o6_ft data bit 6 for m p if not multiplexed 108 d7 i/o6_ft data bit 7 for m p if not multiplexed 109 d8 i/o6_ft data bit 8 for m p if not multiplexed 110 d9 i/o6_ft data bit 9 for m p if not multiplexed 111 d10 i/o6_ft data bit 10 for m p if not multiplexed pin n symbol type function type ft: five volts tolerant fnt: five volts not tolerant ttl i1_ft = input ttl i2_ft = i1_ft+pull up i3_ft = i1_ft+hysteresis i4_ft = i3_ft+pull up ttl i/o6 _ft = input ttl/ output ttl 6 ma i5_ft = i3_ft+pull down; ttl o3 _ft = output ttl 3 ma o3t_ft = o3_ft+tristate o6_ft = output ttl 6ma ttl o6d_ft = output ttl 6ma, open drain o6dt_ft = output ttl 6ma, open drain or tristate cmos i/o8_fnt = input ttl, /output cmos 8ma; o8t_fnt = output cmos 8ma i/o8_fnt = input ttl, /output cmos 8ma cmos o4_fnt = output cmos 4ma
11/130 STLC5466 112 d11 i/o6_ft data bit 11 for m p if not multiplexed 113 d12 i/o6_ft data bit 12 for m p if not multiplexed 114 d13 i/o6_ft data bit 13 for m p if not multiplexed 115 d14 i/o6_ft data bit 14 for m p if not multiplexed 116 d15 i/o6_ft data bit 15 for m p if not multiplexed memory interface 119 tri i3_ft token ring input (for use multi-hdlc s in cascade) 120 tro o4_fnt token ring output (for use multi-hdlc s in cascade) 121 nwe o8t_fnt write enable for sdram 122 nras o8t_fnt row address strobe for sdram 123 nce0 o8t_fnt chip select 0 for sdram 124 ldqm o8t_fnt lower data inputs/outputs mask enable for sdram 125 nce1 o8t_fnt chip select 1 for sdram 126 udqm o8t_fnt upper data inputs/outputs mask enable for sdram 127 nce2/ adm12 o8t_fnt chip select 2 for sdram/ address bit 12 for 8mx8 sdram circuit 129 nce3/adm13 o8t_fnt chip select 3 for sdram/address bit 13 for 8mx8 sdram circuit 137 adm0 o8t_fnt address bit 0 for sdram 138 adm1 o8t_fnt address bit 1 for sdram 139 adm2 o8t_fnt address bit 2 for sdram 140 adm3 o8t_fnt address bit 3 for sdram 141 adm4 o8t_fnt address bit 4 for sdram 142 adm5 o8t_fnt address bit 5 for sdram 143 adm6 o8t_fnt address bit 6 for sdram 144 adm7 o8t_fnt address bit 7 for sdram 145 adm8 o8t_fnt address bit 8 for sdram 146 adm9 o8t_fnt address bit 9 for sdram 149 adm10 o8t_fnt address bit 10 for sdram 150 adm11 o8t_fnt address bit 11 for sdram 151 ncas o8t_fnt column address strobe for sdram 152 scanm i5_ft scan mode reserved for device test 154 dm0 i/o8_fnt sdram data bit 0 155 dm1 i/o8_fnt sdram data bit 1 156 dm2 i/o8_fnt sdram data bit 2 157 dm3 i/o8_fnt sdram data bit 3 158 dm4 i/o8_fnt sdram data bit 4 161 dm5 i/o8_fnt sdram data bit 5 pin n symbol type function type ft: five volts tolerant fnt: five volts not tolerant ttl i1_ft = input ttl i2_ft = i1_ft+pull up i3_ft = i1_ft+hysteresis i4_ft = i3_ft+pull up ttl i/o6 _ft = input ttl/ output ttl 6 ma i5_ft = i3_ft+pull down; ttl o3 _ft = output ttl 3 ma o3t_ft = o3_ft+tristate o6_ft = output ttl 6ma ttl o6d_ft = output ttl 6ma, open drain o6dt_ft = output ttl 6ma, open drain or tristate cmos i/o8_fnt = input ttl, /output cmos 8ma; o8t_fnt = output cmos 8ma i/o8_fnt = input ttl, /output cmos 8ma cmos o4_fnt = output cmos 4ma
STLC5466 12/130 notes : 1. d0/15 input/output pins must be connected to one single external pull up resistor if not used. i.1 - pin definition the pins of the circuit are five volts tolerant except the pins assigned to sdram interface. i.1.1 - input pin definition i.1.2 - output pin definition moreover, each output is high impedance when the ntest pin is at 0 volt. i.1.3 - input/output pin definition. 162 dm6 i/o8_fnt sdram data bit 6 163 dm7 i/o8_fnt sdram data bit 7 164 dm8 i/o8_fnt sdram data bit 8 165 dm9 i/o8_fnt sdram data bit 9 166 dm10 i/o8_fnt sdram data bit 10 167 dm11 i/o8_fnt sdram data bit 11 168 dm12 i/o8_fnt sdram data bit 12 169 dm13 i/o8_fnt sdram data bit 13 170 dm14 i/o8_fnt sdram data bit 14 171 dm15 i/o8_fnt sdram data bit 15 174 ntest i2_ft test control. when this pin is at 0v each output is high impedance. pin n symbol type function type ft: five volts tolerant fnt: five volts not tolerant ttl i1_ft = input ttl i2_ft = i1_ft+pull up i3_ft = i1_ft+hysteresis i4_ft = i3_ft+pull up ttl i/o6 _ft = input ttl/ output ttl 6 ma i5_ft = i3_ft+pull down; ttl o3 _ft = output ttl 3 ma o3t_ft = o3_ft+tristate o6_ft = output ttl 6ma ttl o6d_ft = output ttl 6ma, open drain o6dt_ft = output ttl 6ma, open drain or tristate cmos i/o8_fnt = input ttl, /output cmos 8ma; o8t_fnt = output cmos 8ma i/o8_fnt = input ttl, /output cmos 8ma cmos o4_fnt = output cmos 4ma i1_ft input ttl, five volts tolerant i2_ft input 1 ttl + pull up, five volts tolerant i3_ft input 2 ttl + hysteresis, five volts tolerant i4_ft input 3 ttl + hysteresis +pull up, five volts tolerant. i5_ft input 4 ttl + hysteresis +pull down, five volts tolerant o3_ft output ttl 3 ma, five volts tolerant o3t_ft output ttl 3 ma, tristate, five volts tolerant o6_ft output ttl 6ma, five volts tolerant o6d_ft output ttl 6ma,open drain, five volts tolerant o6dt_ft output ttl 6ma,open drain or tristate. (programmable pin), five volts tolerant o4_fnt output cmos 4ma, five volts not tolerant o8t_fnt output cmos 8ma, tristate, five volts not tolerant i/o6_ft input ttl/ output ttl 6 ma five volts tolerant i/o8_fnt input ttl/output cmos 8ma, five volts not tolerant
13/130 STLC5466 ii - block diagram the top level functionalities of multi-hdlc appear on the general block diagram. there are: C the switching matrix, C the 2 time slot assigners, C the 2 x 32 hdlc transmitters with associated dma controllers, C the 2 x 32 hdlc receivers with associated dma controllers, C the 16 command/indicate and monitor channel transmitters belonging to the two general com- ponent interfaces (gci), C the 16 command/indicate and monitor channel receivers belonging to the two general compo- nent interfaces (gci), C the synchronous dynamic memory interface, C the microprocessor interface including write fifo and fetch memory, C the bus arbitration, C the clock selection and time synchronization function, C the interrupt controller, C the watchdog iii - functional description iii.1 - the switching matrix n x 64 kbits/s iii.1.1 - function description the matrix performs a non-blocking switch of 256 time slots from 8 input time division multiplex (tdm) at 2 mbit/s to 8 output time division multi- plex at 2 mbit/s. a tdm at 2 mbit/s consists of 32 time slots (ts) at 64 kbit/s. one time division multiplex at 4 mbit/s can take place of two time di- vision multiplex at 2 mbit/s. this tdm at 4 mbit/s is composed of 64 time slots (ts) at 64 kbit/s. the matrix is designed to switch a 64 kbit/s chan- nel (variable delay mode) or an hyperchannel of data (sequence integrity mode). so, it will both provide minimum throughput switching delay for voice applications and time slot sequence integrity for data applications on a per channel basis. the requirements of the sequence integrity (n*64 kbit/s) mode are the following: all the time slots of a given input frame must be put out during a same output frame. the time slots of an hyperchannel (concatenation of ts in the same tdm) are not crossed together at output in different frames. in variable delay mode, the time slot is put out as soon as possible. (the delay is two or three time slots minimum between input and output). for test facilities, any time slot of an output tdm (otdm) can be internally looped back into the same input tdm number (itdm) at the same time slot number. a pseudo random sequence generator and a pseudo random sequence analyser are imple- mented in the matrix. they allow the generation of a sequence on a channel or on a hyperchannel, to analyse it and verify its integrity after several switching in the matrix or some passing of the se- quence across different boards. the frame signal (fs) synchronises itdm and otdm but a programmable delay or advance can be introduced separately on each itdm and otdm (a half bit time, a bit time or two bit times). an additional pin ( pss) permits the g eneration of a programmable signal composed of 256 bits per frame at a bit rate of 2048 kbit/s. the programma- tion of this signal is performed thanks to ps bit of connection memory. an external pin (ndis) asserts a high impedance on all the tdm outputs of the matrix when active (during the initialization of the board for example). iii.1.2 - architecture of the matrix the matrix is essentially composed of buffer data memories and a connection memory. the received serial data is first converted to paral- lel by a serial to parallel converter and stored con- secutively in a 256 position buffer data memory (see figure). to satisfy the sequence integrity (n*64 kbit/s) re- quirements, the data memory is built with an even memory, an odd memory and an output memory. two consecutive frames are stored alternatively in the odd and even memory. during the time an in- put frame is stored, the one previously stored is transferred into the output memory according to the connection memory switching orders. a frame later, the output memory is read and data is con- verted to serial and transferred to the output tdm. iii.1.3 - connection function two types of connections are offered: C unidirectional connection and C bidirectional connection. an unidirectional connection makes only the switch of an input time slot through an output one whereas a bidirectional connection establishes the link in the other direction too. so a double connec- tion can be achieved by a single command (see figure).
STLC5466 14/130 figure 1 : block diagram dout 4 din 4 din 2 din 1 din 0 dout 3 dout 2 dout 1 dout 0 din 7 din 5 din 6 din 3 dout 6 dout 5 dout 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 d7 gci0 gci1 v10a v10a gci0 gci1 ndis tx gci v10b din 9 din 8 cb1 ec1 cb2 ec2 7 d6 v10a v10b v10b switching matrix n x 64 kb/s scrambler/descrambler for 32 channels pseudo random sequence analyser pseudo random sequence generator first 32 rx hdlc with address recognition 32 rx dmac second 32 rx hdlc with address recognition 32 rx dmac second 32 tx hdlc with csma cr for contention bus 32 tx dmac first 32 tx hdlc with csma cr for contention bus 32 tx dmac bus arbitration first time slot assigner second time slot assigner rx gci internal bus microprocessor interface sdram controller v10a, bit v10 of tadr1 v10b, bit v10 of tadr2 d6, bit of gcr2 d7, bit of gcr1
15/130 STLC5466 iii.1.4 - loop back function any time slot of an output tdm can be internally looped back on the time slot which has the same tdm number and the same ts number (otdmi, tsj) ----> (itdmi, tsj). in the case of a bidirectional connection, only the one specified by the microprocessor is concerned by the loop back (see figure). iii.1.5 - delay through the matrix iii.1.5.1 - variable delay mode in the variable delay mode, the delay through the matrix depends on the relative positions of the in- put and output time slots in the frame. so, some limits are fixed: C the maximum delay is a frame + 2 time slots, C the minimum delay is programmable. three time slots if imtd = 1, in this case n = 2 in the formula hereafter or two time slots if imtd = 0, in this case n = 1 in the same formula (see paragraph switching matrix configuration register smcr (0c) h ). all the possibilities can be ranked in three cases: a) if otsy > itsx + n then the variable delay is: otsy - itsx time slots b) if itsx < otsy < itsx+n then the variable delay is: otsy - itsx + 32 time slots c) otsy < itsx then the variable delay is: 32 - (itsx - otsy) time slots. n.b. rule b) and rule c) are identical. for n = 1 and n = 2, (see figure). iii.1.5.2 - sequence integrity mode in the sequence integrity mode (si = 1, bit located in the connection memory), the input time slots are put out 2 frames later (see figure). in this case, the delay is defined by a single expression: constant delay = (32 - itsx) + 32 + otsy so, the delay in sequence integrity mode varies from 33 to 95 time slots. iii.1.6 - connection memory iii.1.6.1 - description the connection memory is composed of 256 loca- tions addressed by the number of otdm and ts (8x32). each location permits: C to connect each input time slot to one output time slot (if two or more output time slots are connected to the same input time slot number, there is broadcasting). C to select the variable delay mode or the se- quence integrity mode for any time slot. C to loop back an output time slot. in this case the contents of an input time slot (itsx, itdmp) is the same as the output time slot (otsx, ot- dmp). C to output the contents of the corresponding con- nection memory instead of the data which has been stored in data memory. C to output the sequence of the pseudo random sequence generator on an output time slot: a pseudo random sequence can be inserted in one or several time slots (hyperchannel) of the same output tdm; this insertion must be ena- bled by the microprocessor in the configuration register of the matrix. C to define the source of a sequence by the pseu- do random sequence analyser: a pseudo ran- dom sequence can be extracted from one or several time slots (hyperchannel) of the same input tdm and routed to the analyser; this ex- traction can be enabled by the microprocessor in the configuration register of the matrix (sm- cr). C to assert a high impedance level on an output time slot (disconnection). C to deliver a programmable 256-bit sequence during 125 microseconds on the programmable synchronization signal pin ( pss). iii.1.6.2 - access to connection memory supposing that the switching matrix configuration register (smcr) has been already written by the microprocessor, it is possible to access to the con- nection memory from microprocessor with the help of two registers: C connection memory data register (cmdr) and C connection memory address register (cmar). iii.1.6.3 - access to data memory to extract the contents of the data memory it is possible to read the data memory from microproc- essor with the help of the two registers: C connection memory data register (cmdr) and C connection memory address register (cmar). iii.1.7 - switching at 32 kbit/s four tdms can be programmed individually to carry 64 channels at 32 kbit/s (only if these tdms are at 2 mbit/s). two bits (sw0/1) located in smcr define the type of channels of two couples of tdms. sw0 defines tdm0 and tdm4 (gci0) and sw1 defines tdm1 and tdm5 (gci1). if tdm0 or/and tdm1 carry 64 channels at 32
STLC5466 16/130 kbit/s then tdm2 or/and tdm3 are not available externally they are used internally to perform the function. see figure: downstream switching at 32 kb/s. see figure: upstream switching at 32 kb/s. iii.1.8 - switching at 16 kbit/s the tdm4 and tdm5 can be gci multiplexes. each gci multiplex comprises 8 gci channels. each gci channel comprises one d channel at 16 kbit/s. see figure: gci channel definition, gci synchro signal delivered by the multi-hdlc it is possible to switch the contents of 16 d chan- nels from the 16 gci channels to 4 timeslots of the 256 output timeslots. in the other direction the contents of an selected timeslot is automatically switched to 4 d channels at 16 kbit/s. see connection memory data register cmdr (0e)h. iii.2 - hdlc controller iii.2.1 - function description two independent hdlc controllers allow to proc- ess 64 channels. each internal hdlc controller can run up to 32 channels in a conventional hdlc mode or in a transparent (non-hdlc) mode (configurable per channel). each channel bit rate is programmable from 4kbit/ s to 64kbit/s. all the configurations are also possi- ble from 32 channels (from 4 to 64 kbit/s) to one channel at 2 mbit/s. C first hdlc controller in reception for the first hdlc controller, the con- tents of each time slot can directly come from the input tdm din8 (direct hdlc input) or from any other tdm input after switching towards the output 7 of the matrix (configurable per time slot). in transmission, the hdlc frames are sent on the output dout6 and on the output cb1 (with or without contention mechanism), or are switched towards the other tdm output via the input 7 of the matrix. C second hdlc controller in reception for the second hdlc controller, the contents of each time slot can directly come from the input tdm din9 (direct hdlc input) or from any other tdm input after switching towards the output 6 of the matrix (configurable per time slot). in transmission, the hdlc frames are sent on the output dout7 and on the output cb2 (with or without contention mechanism), or are switched towards the other tdm output via the input 6 of the matrix. iii.2.1.1 - format of the hdlc frame the format of an hdlc frame is the same in re- ceive and transmit direction and shown here after. iii.2.1.2 - composition of an hdlc frame C opening flag C one or two bytes for address recognition (recep- tion) and insertion (transmission) C data bytes with bit stuffing C frame check sequence: crc with polynomial g(x) = x 16 +x 12 +x 5 +1 C closing flag. iii.2.1.3 - description and functions of the hdlc bytes Cflag the binary sequence 01111110 marks the be- ginning and the end of the hdlc frame. note: in reception, three possible flag configura- tion are allowed and correctly detected: - two normal consecutive flags: ...01111110 01111110... - two consecutive flags with a 0 common: ...011111101111110... - a global common flag:...01111110... this flag is the closing flag for the current frame and the opening flag for the next frame C abort the binary sequence 1111111 marks an abort command. in reception, seven consecutive 1s, inside a message, are detected as an abort command and generates an interrupt to the host. in transmit direction, an abort is sent upon com- mand of the micro-processor. no ending flag is expected after the abort command. opening flag address field (first byte) address field (second byte) command field (first byte) command field (second byte) data (first byte) data (optional) data (last byte) fcs (first byte) fcs (second byte) closing flag
17/130 STLC5466 C bit stuffing and unstuffing this operation is done to avoid the confusion of a data byte with a flag. in transmission, if five consecutive 1s appear in the serial stream being transmitted, a zero is au- tomatically inserted (bit stuffing) after the fifth 1. in reception, if five consecutive 1 followed by a zero are received, the 0 is assumed to have been inserted and is automatically deleted (bit unstuffing). C frame check sequence the frame check sequence is calculated ac- cording to the recommendation q921 of the ccitt. C address recognition in the frame, one or two bytes are transmitted to indicate the destination of the message. two types of addresses are possible: - a specific destination address - a broadcast address. in reception, the controller compares the receive addresses to internal registers, which contain the address message. 4 bits in the receive com- mand register (hrcr) inform the receiver of which registers, it has to take into account for the comparison. the receiver compares the two ad- dress bytes of the message to the specific board address and the broadcast address. upon an address match, the address and the data follow- ing are written to the data buffers; upon an ad- dress mismatch, the frame is ignored. so, it authorizes the filtering of the messages. if no comparison is specified, each frame is received whatever its address field. in transmission, the controller sends the frame including the destination or broadcast address- es. iii.2.2 - csma/cr capability an hdlc channel can come in and go out by any tdm input on the matrix. for time constraints, direct hdlc access is achieved by the input tdm (din 8 for the first hdlc controller and din9 for the second hdlc controller) and the output tdm (dout6 for the first and dout7 for the second hdlc controller). in transmission, a time slot of a tdm can be shared between different sources in multi-point to point configuration (different subscribers boards for example). the arbitration system is the csma/ cr (carrier sense multiple access with conten- tion resolution). the contention is resolved by a bus connected to the cb1 pin (contention bus) for the first hdlc controller and cb2 pin for the second hdlc con- troller. these two bus are respectively a 2mbit/s wire line common to all the potential sources. if the first hdlc controller (or the second) has ob- tained the access to the bus, the data to transmit is sent simultaneously on the cb1 line (or the cb2 line) and the output tdm. the result of the conten- tion is read back on the echo line (ec1or ec2). if a collision is detected, the transmission is stopped immediately. a contention on a bit basis is so achieved. each message to be sent with csma/ cr has a priority class (pri = 8, 10) indicated by the transmit descriptor and some rules are imple- mented to arbitrate the access to the line. the csma/cr algorithm is given. when a request to send a message occurs, the transmitter deter- mines if the shared channel is free. the multi- hdlc listens to the echo line. if c or more consec- utive 1 are detected (c depending on the mes- sages priority), the multi-hdlc begins to send its message. each bit sent is sampled back and com- pared with the original value to send. if a bit is dif- ferent, the transmission is instantaneously stopped (before the end of this bit time) and will re- start as soon as the multi-hdlc will detect that the channel is free without interrupting the microproc- essor. after a successful transmission of a message, a programmable penalty pen(1 or 2) is applied to the transmitter. it guarantees that the same trans- mitter will not take the bus another time before a transmitter which has to send a message of same priority. in case of a collision, the frame which has been aborted is automatically retransmitted by the dma controller without warning the microprocessor of this collision. the frame can be located in several buffers in external memory. the collision can be detected from the second bit of the opening frame to the last but one bit of the closing frame. iii.2.3 - time slot assigner memory each hdlc channel is bidirectional and is defined by two time slot assigners (tsa). tsa is a memory of 32 words (one per physical time slot) where all of the 32 input and output time slots of the hdlc controllers can be associated to logical hdlc channels. super channels are creat- ed by assigning the same logical channel number to several physical time slots. the following features are programmed for each hdlc time slot: C time slot used or not C one logical channel number C its source: - din 8 or the output 7 of the matrix for the first time slot assigner
STLC5466 18/130 - din 9 or the output 6 of the matrix for the sec- ond time slot assigner. C its bit rate and concerned bits (4kbit/s to 64kbit/ s). 4kbit/s correspond to one bit transmitted each two frames. this bit is repeated twice in transmission. this bit must be present in two consecutive frames in reception. C its destination for the first time slot assigner: - direct output on dout6 - direct output on dout6 and on the contention bus (cb1) - on another otdm via input 7 of the matrix and on the contention bus (cb1) C its destination for the second time slot assign- er: - direct output on dout7 - direct output on dout7 and on the contention bus (cb2) - on another otdm via input 6 of the matrix and on the contention bus (cb2) iii.2.4 - data storage structure data associated with each rx and tx hdlc chan- nel is stored in external memory; the data trans- fers between the hdlc controllers and memory are ensured by 2*32 dmac (direct memory ac- cess controller) in reception and 2*32 dmac in transmission. the storage structure chosen in both directions is composed of one circular queue of buffers per channel. in such a queue, each data buffer is pointed to by a descriptor located in external memory too. the main information contained in the descriptor is the address of the data buffer, its length and the address of the next descriptor; so the descriptors can be linked together. this structure allows to: C store receive frames of variable and unknown length C read transmit frames stored in external memory by the host C easily perform the frame relay function. iii.2.4.1 - reception at the initialization of the application, the host has to prepare two initialization block registers. each initialization block located in shared memory con- tains the first receive buffer descriptor address for each channel, and the receive circular queues. at the opening of a receive channel, the dma con- troller reads the address of the first buffer descrip- tor corresponding to this channel in the initialization block. then, the data transfer can oc- cur without intervention of the processor. a new hdlc frame always begins in a new buffer. a long frame can be split between several buffers if the buffer size is not sufficient. all the information concerning the frame and its location in the circu- lar queue is included in the receive buffer de- scriptor: C the receive buffer address (rba), C the size of the receive buffer (sob), C the number of bytes written into the buffer (nbr), C the next receive descriptor address (nrda), C the status concerning the receive frame, C the control of the queue. iii.2.4.2 - transmission in transmission, the data is managed by a similar structure as in reception by the same way, a frame can be split up between consecutive transmit buffers. the main information contained in the transmit descriptor are: C transmit buffer address (tba), C number of bytes to transmit (nbt) concerning the buffer, C next transmit descriptor address (ntda), C status of the frame after transmission, C control bit of the queue, C csma/cr priority (8 or 10). iii.2.4.3 - frame relay the principle of the frame relay is to transmit a frame which has been received without treatment. a new heading is just added. this will be easily achieved, taking into account that the queue struc- ture allows the transmission of a frame split be- tween several buffers. iii.2.5 - transparent modes in the transparent mode, the multi-hdlc transmits data in a completely transparent manner without performing any bit manipulation or flag insertion. the transparent mode is per byte function; the channel used for this mode is n*64kb/s mandato- ry. two transparent modes are offered: C first mode: for the receive channels, the multi- hdlc continuously writes received bytes (from the received timeslot) into the external memory as specified in the current receive descriptor without taking into account the fill character register. C second mode: the fill character register spec- ifies the fill character which must be taken into account. in reception, the fill character is de-
19/130 STLC5466 tected in each timeslot and will not be trans- ferred to the external memory. the detection of fill character marks the end of a message and generates an interrupt if bint=1). when the fill character is not detected a new message is re- ceiving. as for the hdlc mode the correspondence be- tween the physical time slot and the logical chan- nel is fully defined in the two time slot assigners (time slot used or not used, logical channel number, source, destination). iii.2.6 - command of the hdlc channels the microprocessor is able to control each hdlc receive and transmit channel. some of the com- mands are specific to the transmission or the re- ception but others are identical. iii.2.6.1 - reception control C the configuration of the controller operating mode is: hdlc mode or transparent mode. C the control of the controller: start, halt, continue, abort. start: on a start command, the rxdma con- troller reads the address of the first descriptor in the initialization block memory and is ready to receive a frame. halt: for overloading reasons, the microproc- essor can decide to halt the reception. the dma controller finishes transfer of the current frame to external memory and stops. the channel can be restarted on continue command. continue: the reception restarts in the next descriptor. abort: on an abort command, the reception is instantaneously stopped. the channel can be restarted on a start or continue command. C reception of flag (01111110) or idle (11111111) between frames. C address recognition. the microprocessor de- fines the addresses that the rx controller has to take into account. C in transparent mode: fill character register is selected or not. iii.2.6.2 - transmission control C the configuration of the controller operating mode is: hdlc mode or transparent mode. C the control of the controller: start, halt, continue, abort. start: on a start command, the tx dma con- troller reads the address of the first descriptor in the initialization block memory and tries to trans- mit the first frame if end of queue is not at 1. halt: the transmitter finishes to send the cur- rent frame and stops.the channel can be re- started on a continue command. continue: if the continue command occurs after halt command, the hdlc transmitter re- starts by transmitting the next buffer associated to the next descriptor. if the continue command occurs after an abort command which has occurred during a frame, the hdlc transmitter restarts by trans- mitting the frame which has been effectively aborted by the microprocessor. abort: on an abort command, the transmis- sion of the current frame is instantaneously stopped, an abort sequence 1111111 is sent, followed by idle or flag bytes. the channel can be restarted on a start or con- tinue command. C transmission of flag (01111110) or idle (111111111) between frames can be selected. C crc can be generated or not. if the crc is not generated by the hdlc controller, it must be lo- cated in the shared memory. C in transparent mode: fill character register can be selected or not. iii.3 - c/i and monitor iii.3.1 - function description the multi-hdlc is able to operate both gci and v* links. the tdm din/dout 4 and 5 are internal- ly connected to the ci and monitor receivers/trans- mitters. since the controllers handle up to 16ci and 16 monitor channels simultaneously, the mul- ti-hdlc can manage up to 16 level 1 circuits. the multi-hdlc can be used to support the ci and monitor channels based on the following proto- cols: C isdn v* protocol C isdn gci protocol C analog gci protocol. iii.3.2 - gci and v* protocol a tdm can carry 8 gci channels or v* channels. the monitor and s/c bytes always stand at the same position in the tdm in both cases. cgi channel 0 cgi channel 1 to channel 6 cgi channel 7 ts0 ts1 ts2 ts3 ts28 ts29 ts30 ts31 b1 b2 mon s/c b1 b2 mon s/c
STLC5466 20/130 the gci or v* channels are composed of 4 bytes and have both the same general structure. only monitor handshakes and s/c bytes are dif- ferent in the three protocols: isdn v* s/c byte isdn gci s/c byte analog gci s/c byte in gci protocol, a and e are the handshake bits and are used to control the transfer of information on monitor channels.the e bit indicates the trans- fer of each new byte in one direction and the a bit acknowledges this byte transfer in the reverse di- rection. in v* protocol, there isnt any handshake mode.the transmitter has only to mark the validity of the monitor byte by positioning the e bit (t is not used and is forced to 1). for more information about the gci and v*, refer to the general interface circuit specification (issue1.0, march 1989) and the france telecom specification about isdn basic access second generation (november 1990). iii.3.3 - structure of the treatment in reception gci/v* tdms are connected to din 4 and din 5. the d channels are switched through the matrix towards the output 7 and output6 then towards the hdlc receivers. the monitor and s/c bytes are multiplexed and sent to the ci and mon- itor receivers. in transmission, the s/c and monitor bytes are re- combined by multiplexing the information provided by the monitor, c/i and the hdlc transmitter. like in reception, the d channel is switched through the matrix (input 7 towards dout 4 and dout 5). iii.3.4 - ci and monitor channel configuration monitor channel data is located in a time slot; the ci and monitor handshake bits are in the next time slot. each channel can be defined independently. a ta- ble with all the possible configurations is present- ed hereafter (table 13). table 13: c/i and mon channel configuration note: a mix of v* and gci monitoring can be performed for two dis- tinct channels in the same application. iii.3.5 - ci and monitor transmission/reception command the reception of c/i and monitor messages are managed by two interrupt queues. in transmission, a transmit command register is implemented for each c/i and monitor channel (16c/i transmit command registers and 16 monitor transmit command registers). those registers are accessible in read and write modes by the micro- processor. iii.4 - scrambler and descrambler the tdm4 and tdm5 can be gci multipexes. each gci multipex comprises 8 gci channels. each gci channel comprises two b channels at 64 kbit/s. in reception it is possible to switch and to scramble the contents of 32 b channels of gci channels to 32 timeslots of the 256 output timeslots. in trans- mission these 32 timeslots are assigned to 32 b channels. in the other direction the contents of an selected b channels is automatically switched and descram- bled to one b channel of 16 gci channel. see scr bit of connection memory data register cmdr (0e)h. iii.5 - connection between isdn channels and gci channels. three timeslots are assigned to one isdn chan- nels. each isdn channels comprises three channels: b1+b2+b* with b*= d1,d2, a, e, s1, s2, s3, s4 (see figure). C upstream. from gci channels to isdn chan- nels. ? in reception: 16 gci channels (b1+b2+mon+ d+c/i), b1 b2 mon s/c b1, b2 : bytes of data. those bytes are not af- fected by the monitor and ci protocols. mon : monitor channel for operation and maintenance information. s/c : signalling and control information. d 2 bits c/i 4 bits t e d 2 bits c/i 4 bits a e c/i 6 bits a e ci : the command/indicate channel is used for activation/deactivation of lines and control functions. d : these 2 bits carry the 16 kbit/s isdn basic access d channel. c/i validated or not ci for analog subscriber (6 bits) ci for isdn subscriber (4 bits) monitor validated or not monitor v* monitor gci
21/130 STLC5466 ? in transmission: 16 isdn channels (b1+b2+b*). it is possible to switch the contents of b1, b2 and d channels from 16 gci channels in any 16 isdn channels, tdm side. the contents of b1 and/or b2 can be scrambled or not. if scrambled the number of the 32 timeslots (tdm side) are different mandatory. receiving the contents of monitor and command / indicate channels from 16 gci channels. primi- tives and messages are stored automatically in the external shared memory. transmitting six bit word (a, e, s1, s2, s3, s4) to any 16 isdn channels tdm side or not. see sbv bit of general configuration register gcr (02)h. C downstream. from isdn channels to gci chan- nels. ? in reception: isdn channel (b1+b2+b*) ? in transmission: gci channel (b1+b2+mon+ d+c/i) it is possible to switch the contents of b1, b2 and d channels from 16 isdn channels, tdm side in 16 gci channels. the contents of b1 and/or b2 can be descrambled or not. if descrambled the 32 b1/b2 belong to gci channels mandatory. receiving six bit word (a, e, s1, s2, s3, s4) from any 16 isdn channels, tdm side. the 16 six bit word are stored automatically in the external shared memory. transmitting the contents of monitor and com- mand / indicate channels to 16 gci channels. see sbv bit of general configuration register gcr (02)h. C alarm indication signal. this detection concerns 16 hyperchannels. one hyperchannel comprises 16 bits (b1 and b2 only). the alarm indications for the 16 hyperchannels are stored automatically in the external shared memory. see aisd bit of switching matrix config- uration register smcr (0c)h. iii.6 - microprocessor interface iii.6.1 - description the multi-hdlc circuit can be controlled by sever- al types of microprocessors (st9/10, intel/motoro- la 8 or 16 data bits interfaces) such as: C st9/10 family C intel 80c188 8 bits C intel 80c186 16 bits C intel 386ex 16 bits C motorola 68000 16 bits C motorola 68020 32 bits table 14: microprocessor interface selection during the initialization of the multi-hdlc circuit, the microprocessor interface is informed of the type of microprocessor that is connected by polar- isation of three external pins mod 0/2. three chip select (cs0/2) pins are provided. cs0 will select the internal registers and cs1 the exter- nal memory. cs2 can be used to select the exter- nal memory in intel 386ex application only (see pin 41 definition). iii.6.2 - buffer a buffer is located in the microprocessor interface. it is used whatever microprocessor selected thanks to mod0/2 pins. it allows to reduce the shared memory access cycles for the microproc- essor. this buffer consists of one write fifo and one read fetch memory (see figure). iii.6.2.1 - write fifo when the microprocessor delivers the address word named ax to write data named [ax] in the shared memory in fact it writes data [ax] and ad- dress word ax in the write fifo (8 words). if ax is in fetch memory, [ax] is removed in fetch memo- ry. there is no wait time for the microprocessor if the write fifo is not full entirely. mod2 pin mod1 pin mod0 pin microprocessor 0 1 1 80c188 1 1 1 80c186 1 0 0 68000 0 0 0 68020 0 0 1 st9 1 0 1 st10 a/d multiplexed 1 1 0 st10 a/d not multiplexed 0 1 0 386ex
STLC5466 22/130 shared memory sdram bus to shared memory sdram controller from shared memory mhdlc internal bus ax, [ax] read fetch 64 words fetch memory an, [an] ay, [ay] memory az, [az] at, [at] write fifo up to eight words input register used to store data in write fifo from microprocessor mhdlc microprocessor interface to microprocessor microprocessor bus microprocessor figure 2 : exchange between microprocessor and shared memory across mhdlc
23/130 STLC5466 iii.6.2.2 - read fetch memory when the microprocessor delivers the address word named an to read data named [an] out of the shared memory in fact it reads data [an] from the read fetch memory (64 words). the number of wait cycle for the microprocessor is strongly reduced. if an, address word delivered by the microprocessor, and data [an] are already in the read fetch memory and validated then there is no wait time for the microprocessor. the source of [an] is truly the shared memory whatever an. data [an] if validated in fetch memory and data [an] in shared memory are always the same. iii.6.2.3 - definition of the interface for the dif- ferent microprocessors the signals connected to the microprocessor in- terface are presented on the following figures for the different microprocessor (see figures). iii.7 - memory interface iii.7.1 - function description the memory interface allows the connection of synchronous dynamic ram. the memory inter- face will address up to 16 megabytes. the memo- ry location is always organized in 16 bits. the memory is shared between the multi-hdlc and the microprocessor. the access to the mem- ory is arbitrated by an internal function of the cir- cuit: the bus arbitration. iii.7.2 - choice of memory versus microproces- sor and capacity required the memory interface depends on the memory chips which are connected. the memory chips will be chosen versus their organization. example1: if the application requires 8 or 16 bit m processor and 1 megaword shared memory size, one capability is offered: C 1 sdram circuit (1mx16). example2: if the application requires 16 bit m proc- essor and 4 megaword shared memory size, three capabilities are offered: C 4 sdram circuits (1mx16) or C 4 sdram circuits (4mx4) or C 1 sdram circuit (4mx16). .example3: if the application requires 8 megaword shared memory size three capabilities are offered: C 8 sdram circuits (4mx4) or C 2 sdram circuits (4mx16) or C 2 sdram circuit (8mx8). iii.7.3 - memory cycle some parameters are frozen: C burst read and single write. C the burst length is 4. C the burst data is addressed in sequential mode. the programmable parameters are: C latency mode C selected circuit organisation C the exchanges between multi-hdlc and sdram are at the master clock frequency (33mhz, 50mhz, 66mhz) iii.7.4 - memories composed of different cir- cuits iii.7.4.1 - memory obtained with 1m x16 sdram circuit the address bits delivered by the multi-hdlc for 1m x 16 sdram circuits are: C adm11 for bank select corresponding with a20 delivered by the microprocessor C adm0/10 for row address inputs corresponding with a9/19 delivered by the microprocessor C adm0/7 for column address inputs correspond- ing with a1/8 delivered by the microprocessor iii.7.4.2 - memory obtained with 2m x 8 sdram circuit the address bits delivered by the multi-hdlc for 2m x 8 sdram circuits are: C adm11 for bank select corresponding with a21 delivered by the microprocessor C adm0/10 for row address inputs corresponding with a10/20 delivered by the microprocessor C adm0/8 for column address inputs correspond- ing with a1/9 delivered by the microprocessor signals a22 a21 signals a0 or equiva- lent nce3 1 1 nce2 1 0 nce1 0 1 udqm 1 nce0 0 0 ldqm 0 signals a0 or equivalent nlds nuds udqm 1 0 1 ldqm 0 1 0
STLC5466 24/130 iii.7.4.3 - memory obtained with 8m x 8 sdram circuit the address bits delivered by the multi-hdlc for 8m x 8 sdram microprocessor circuits are: C adm12/13 for bank select corresponding with a22/23 delivered by the microprocessor C adm0/11 for row address inputs corresponding with a10/21 delivered by the microprocessor C adm0/8 for column address inputs correspond- ing with a1/9 delivered by the microprocessor iii.7.4.4 - memory obtained with 4m x 16 sdram circuit the address bits delivered by the multi-hdlc for 4m x 16 sdram circuits are: C adm12/13 for bank select corresponding with a21/22 delivered by the microprocessor C adm0/11 for row address inputs corresponding with a9/20 delivered by the microprocessor C adm0/7 for column address inputs correspond- ing with a1/8 delivered by the microprocessor iii.8 - bus arbitration the bus arbitration function arbitrates the access to the bus between different entities of the circuit. those entities which can call for the bus are the following: C the receive dma controller, C the microprocessor, C the transmit dma controller, C the interrupt controller, C the memory interface for refreshing the sdram. this list gives the memory access priorities per de- fault. if the treatment of more than 64 hdlc channels is required by the application, it is possible to chain several multi-hdlc components. that is done with two external pins (tri, tro) and a token ring system. the tri, tro signals are managed by the bus ar- bitration function too. when a chip has finished its tasks, it sends a pulse of 30 ns to the next chip. iii.9 - clocks iii.9.1 - clock distribution selection and super- vision two clock distributions are available: clock at 4.096 mhz or 8.192 mhz and a synchro- nization signal at 8 khz. the component has to select one of these two dis- tributions and to check its integrity. two other clock distributions are allowed: clock at 3072 mhz or 6144 mhz and a synchronization sig- nal at 8 khz. see general configuration register gcr (02) h . dclk, fsc gci and fsc v* are output on three external pins of the multi-hdlc. dclk is the clock selected between clock a and clock b. fsc, gci and fsc v* are functions of the selected distribu- tion and respect the gci and v* frame synchroni- zation specifications. the supervision of the clock distribution consists of verifying its availability. the detection of the clock absence is done in a less than 250 microsec- onds. in case the clock is absent, an interrupt is generated with a 4 khz recurrence. then the clock distribution is switched automatically up to detec- tion of couple a or couple b. when a couple is de- tected the change of clock occurs on a falling edge of the new selected distribution. moreover the clock distribution can be controlled by the micro- processor thanks to selb, bit of general configu- ration register. depending on the applications, three different sig- nals of synchronization (gci, v* or sy) can be pro- vided to the component. the clock a/b frequency can be a 4096 or 8192 khz clock. the component is informed of the synchronization and clocks that are connected by software. iii.9.2 - vcxo frequency synchronization an external vcxo can be used to provide a clock to the transmission components. this clock is con- trolled by the main clock distribution (clock a or clock b at 4096khz). as the clock of the transmis- sion component is 15360 or 16384khz, a config- urable function is necessary. the vcxo frequency is divided by p (30 or 32) to provide a common sub-multiple (512khz) of the reference frequency clocka or clockb (4096khz). the comparison of these two signals gives an error signal which commands the vcxo. two external pins are needed to perform this func- tion: vcxo-in and vcxo-out. signals a0 or equivalent nlds nuds udqm 1 0 1 ldqm 0 1 0 signals a23 signals a0 or equiva- lent nlds nuds nce1 1 udqm 1 0 1 nce0 0 ldqm 0 1 0
25/130 STLC5466 iii.10 - interrupt controller iii.10.1 - description three external pins are used to manage the inter- rupts generated by the multi-hdlc . the interrupts have three main sources: C the operating interrupts generated by the hdlc receivers/transmitters, the ci receivers and the monitor transmitters/receivers. int0 pin is re- served for this use. C the interrupt generated by an abnormal working of the clock distribution. int1 pin is reserved for this use. C the non-activity of the microprocessor (watch- dog). wdo pin is reserved for this use. iii.10.2 - operating interrupts (int0 pin) there are five main sources of operating interrupts in the multi-hdlc circuit: C the hdlc receiver, C the hdlc transmitter, C the ci receiver, C the monitor receiver, C the monitor transmitter. when an interrupt is generated by one of these functions, the interrupt controller: C collects all the information about the reasons of this interrupt C stores them in external memory. C informs the microprocessor by positioning the int0 pin in the high level. three interrupt queues are built in external mem- ory to store the information about the interrupts: C a single queue for the hdlc receivers and transmitter C one for the ci receivers C one for the monitor receiver the microprocessor takes the interrupts into ac- count by reading the interrupt register (ir) of the interrupt controller. this register informs the microprocessor of the in- terrupt source. the microprocessor will have infor- mation about the interrupt source by reading the corresponding interrupt queue (see paragraph in- terrupt register ir(38) h on page 74). on an overflow of the circular interrupt queues and an overrun or underrun of the different fifo, the int0pin is activated and the origin of the interrupt is stored in the interrupt register. a 16 bits register is associated with the tx monitor interrupt. it informs the microprocessor of which transmitter has generated the interrupt (see para- graph transmit monitor interrupt register tmir(30) h on page 71). iii.10.3 - time base interrupts (int1 pin) the time base interrupt is generated when an ab- sence or an abnormal working of clock distribution is detected. the int1 pin is activated. iii.10.4 - emergency interrupts (wdo pin) the wdo signal is activated by an overflow of the watchdog register. iii.10.5 - interrupt queues there are three different interrupt queues: C tx and rx hdlc interrupt queue C rx c/i interrupt queue C rx monitor interrupt queue. their length can be defined by software. for debugging function, each interrupt word of the ci interrupt queue and monitor interrupt queue can be followed by a time stamped word. it is com- posed of a counter which runs in the range of 250 m s. the counter is the same as the watchdog counter. consequently, the watchdog function isnt available at the same time. iii.11 - watchdog this function is used to control the activity of the application. it is composed of a counter which counts down from an initial value loaded in the timer register by the microprocessor. if the microprocessor doesnt reset this counter before it is totally decremented, the external pin wdo is activated; this signal can be used to reset the microprocessor and all the application. the initial time value of the counter is programma- ble from 0 to 15s in increments of 0.25ms. at the reset of the component, the counter is auto- matically initialized by the value corresponding to 512ms which are indicated in the timer register. the microprocessor must put wdr (idcr regis- ter) to1 to reset this counter and to confirm that the application started correctly. in the reverse case, the wdo signal could be used to reset the board a second time. iii.12 - reset there are two possibilities to reset the circuit: Cby software, C by hardware. each programmable register receives its default value. after that, the default value of each data register is stored in the associated memory except for time slot assigner memory.
STLC5466 26/130 iii.13 - boundary scan the multi-hdlc is equipped with an ieee stand- ard test access port (ieee std 1149.1). the boundary scan technique involves the inclusion of a shift register stage adjacent to each component pin so that signals at component boundaries can be controlled and observed using scan testing principle. its intention is to enable the test of on board interconnections and asic production tests. the external interface of the boundary scan is composed of the signals tdi, tdo, tck, tms and trst as defined in the ieee st andard.
27/130 STLC5466 iv - dc specifications . absolute maximum ratings symbol parameter value unit v dd 3.3v power supply voltage -0.5v to 4v v input or output voltage -0.5 to v dd + 0.5v v input or output voltage -0.5 to +5.5v(see note 1) v t stg storage temperature -55 to 125 /c /c recommended dc operating conditions symbol parameter min. typ. max. unit v dd 3.3v power supply voltage (see note2) 3.0 3.3 3.6 v t oper operating temperature - 40 85 /c note 1: for 5v tolerant inputs and 5v tolerant output buffers in tristate mode note 2: all the following specifications are valid only within these recommended operating conditions ttl input dc electrical characteristics symbol parameter test conditions min. typ. max. unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v ol low level output voltage i ol = x ma (see note 3) 0.4 v v oh high level output voltage i oh = -x ma (see note 3) 2.4 v i il low level input current without pull-up device v i = 0v 1 m a i ih high level input without pull-up device v i = v dd -1 m a i oz tristate output leakage current without pullup/down device vi = vdd -1 m a vhyst schmitt trigger hysteresis 0.4 0.7 v v t+ positive trigger voltage 0.9 1.35 v v t- negative trigger voltage 0.4 0.7 v note 3: x is the source /sink current under worst case conditions in accordance with the drive capability: o3 = 3ma, o4 = 4 ma cmos output dc electrical characteristics valid only within these recommended operating conditions symbol parameter test conditions min. typ. max. unit v il low level input voltage 0.2v dd v v ih high level input voltage 0.8v dd v v ol low level output voltage iol = xma (see note 4) 0.4 v v oh high level output voltage ioh = xma (see note 4) 0.85v dd v note 4: x is the source/sink current under worst case conditions and is reflected in the name of the i/o cell according to the drive capability. x = 4 or 8ma
STLC5466 28/130 pull-up and pull-down characteristics symbol parameter test conditions min. typ. max. unit ipu pull-up current vi = 0v (note5) -25 -66 -125 m a ipd pull-down current vi = vdd (note5) +25 +66 +125 ua ipd pull-down current vi = 5v (note5) +25 +66 +125 ua rpu equivalent pull-up resistance vi = 0v 50 kohm rpd equivalent pull-down resistance vi = vdd 50 kohm rpd equivalent pull-down resistance vi = 5v (note6) 76 kohm note5 min condition: vdd = 3.0v, 85 degrees c. max condition: vdd = 3.6v, -40 degrees c. note6 for 5v tolerant buffers general interface electrical characteristics symbol parameter test conditions min. typ. max. unit p power dissipation vdd=3.3 volts; mclk=66mhz 350 450 mw cin input capacitance freq = 1mhz@0v (note6) 2 4 pf cout output capacitance (note 7 )4pf c i/o bidir i/o capacitance (note 7 )48pf vesd electrostatic protection c = 100pf, r = 1.5k w 2000 v note7 excluding package (tqfp176, add 1.9pf)
29/130 STLC5466 v - list of registers internal registers ? identification and dynamic command register idcr (00)h ? general configuration register 1 gcr1 (02)h ? input multiplex configuration register 0 imcr0 (04)h ? input multiplex configuration register 1 imcr1 (06)h ? output multiplex configuration register 0 omcr0 (08)h ? output multiplex configuration register 1 omcr1 (0a)h ? switching matrix configuration register smcr (0c)h ? connection memory data register cmdr (0e)h ? connection memory address register cmar (10)h ? sequence fault counter register sfcr (12)h ? time slot assigner address register 1 taar1 (14)h ? time slot assigner data register 1 tadr1 (16)h ? hdlc transmit command register 1 htcr1 (18)h ? hdlc receive command register 1 hrcr1 (1a)h ? address field recognition address register 1 afrar1 (1c)h ? address field recognition data register 1 afrdr1 (1e)h ? fill character register 1 fcr1 (20)h ? gci channels definition register 0 gcir0 (22)h ? gci channels definition register 1 gcir1 (24)h ? gci channels definition register 2 gcir2 (26)h ? gci channels definition register 3 gcir3 (28)h ? transmit command / indicate register tcir (2a)h ? transmit monitor address register tmar (2c)h ? transmit monitor data register tmdr (2e)h ? transmit monitor interrupt register tmir (30)h ? memory interface configuration register micr (32)h ? initiate block address register 1 ibar1 (34)h ? interrupt queue size register iqsr (36)h ? interrupt register ir (38)h ? interrupt mask register imr (3a)h ? timer register 1 timr1 (3c)h ? test register tr (3e)h ? general configuration register 2 gcr2 (42)h ? split fetch memory register sfmr (4e)h ? time slot assigner address register 2 taar2 (54)h ? time slot assigner data register 2 tadr2 (56)h ? hdlc transmit command register 2 htcr2 (58)h ? hdlc receive command register 2 hrcr2 (5a)h ? address field recognition address register 2 afrar2 (5c)h ? address field recognition data register 2 afrdr2 (5e)h ? fill character register 2 fcr2 (60)h ? sdram mode register sdramr (72)h ? initiate block address register 2 ibar2 (74)h ? timer register 2 timr2 (7c)h
STLC5466 30/130 external registers ? initialization block in external memory (iba1 and iba2) ? receive descriptor ? transmit descriptor ? receive & transmit hdlc frame interrupt ? receive command / indicate interrupt ? receive monitor interrupt
31/130 STLC5466 vi - internal registers not used bits (nu) are accessible by the microprocessor but the use of these bits by software is not rec- ommended. reserved bits are not implemented in the circuit. however, it is not recommended to use these bits. vi.1 - identification and dynamic command register idcr (00) h when this register is read by the microprocessor, the circuit code c0/15 is returned. reset has no effect on this register. c0/3 indicates the version. c4/7 indicates the revision. c8/11 indicates the foundry. c12/15 indicates the type. example: this code is (0010) h for the first sample. when this register is written by the microprocessor then: after writing this register, the values of these three bits return to the default value. vi.2 - general configuration register 1 gcr1 (02) h bit15 bit8 bit7 bit0 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 bit15 bit8 bit7 bit0 nu nu nu nu nu nu nu nu nu nu nu nu nu rss wdr tl tl : token launch when tl is set to 1 by the microprocessor, the token pulse is launched from the tro pin (token ring output pin). this pulse is provided to the tri pin (token ring input pin) of the next circuit in the applications where several multi-hdlc s are connected to the same shared memory. wdr : watchdog reset. when the bit 1 (wdr) of this register is set to 1 by the microprocessor, the watchdog counter is reset. rss : reset software when the bit 2 (rss) of this register is set to 1 by the microprocessor, the circuit is reset (same action as reset pin). bit15 bit8 bit7 bit0 sbv mbl afab scl bsel selb csd hcl syn1 syn0 d7 evm tsv trd pma wdd after reset (0000) h wdd : watch dog disable wdd = 1, the watch dog is masked: wdo pin stays at 0. wdd = 0, the watch dog generates an 1 on wdo pin if the microprocessor has not reset the watch dog during the duration programmed in timer register. pma : priority memory access pma = 1, if the token ring has been launched it is captured and kept in order to authorize mem- ory accesses. pma = 0, memory is accessible only if the token is present; after one memory access the token is re-launched from tro pin of the current circuit to tri pin of the next circuit. trd : token ring disable trd = 1, if the token has been launched, the token ring is stopped and destroyed; memory ac- cesses are not possible. the token will not appear on tro pin. trd = 0, the token ring is authorized; when the token will be launched, it will appear on tro pin.
STLC5466 32/130 tsv : time stamping validated tsv = 1, the time stamping counter becomes a free binary counter and counts down from 65535 to 0 in step of 250 microseconds (total = 16384ms). so if an event occurs when the counter indicates a and if the next event occurs when the counter indicates b then: t = (a-b) x 250 microseconds is the time which has passed between the two events which have been stored in memory by the interrupt controller (for rx c/i and rx mon channel only). tsv = 0, the counter becomes a decimal counter.the timer register and this decimal counter constitute a watch dog or a timer. evm : external vcxo mode evm=1,vcxo synchronization counter is divided by 32. evm=0,vcxo synchronization counter is divided by 30. d7 : first hdlc controller connected to matrix d7 = 1, the first transmit hdlc controller is connected to matrix input 7, the din7 signal is ig- nored. d7 = 0, the din7 signal is taken into account by the matrix, the first transmit hdlc controller is ignored by the matrix. syn0/1 : synchronization syn0/1: these two bits define the signal applied on framea/b inputs. hcl : high bit clock this bit defines the signal applied on clocka/b inputs. hcl = 1, bit clock signal is at 8192khz (or 6144khz) hcl= 0, bit clock signal is at 4096khz (or 3072khz) csd : clock supervision deactivation csd = 1, the lack of selected clock is not seen by the microprocessor; int1 is masked. csd = 0, when the selected clock disappears the int1 pin goes to 5v, 250ms after this disappearance. selb : select b selb = 1, frame b and clock b must be selected. selb = 0, frame a and clock a must be selected. bsel : b selected (this bit is read only) bsel = 1, frame b and clock b are selected. bsel = 0, frame a and clock a are selected. scl : single clock this bit defines the signal delivered by dclk output pin. clocka/b inputs at 4096khz or 8192khz scl = 1, data clock is at 2048khz. scl = 0, data clock is at 4096khz. clocka/b inputs at 3072khz or 6144khz scl = 1, data clock is at 1536khz. scl = 0, data clock is at 3072khz. syn1 syn0 signal applied on framea/b inputs 0 0 sy interface 0 1 gci interface (the signal defines the first bit of the frame) 1 0 vstar interface (the signal defines third bit of the frame) 1 1 not used
33/130 STLC5466 vi.3 - input multiplex configuration register 0 imcr0 (04) h see definition in next paragraph. afab : advanced frame a/b signal afab = 1, the advance of framea signal and frameb signal is 0.5 bit time versus the signal framea (or b). afab = 0, framea signal and frameb signal are in accordance with the clock timing. mbl : memory bus low impedance mbl = 1, the shared memory bus is at low impedance between two memory cycles and also at low impedance during a memory cycle. the memory bus includes control bus, address bus except data bus. one multi-hdlc can be connected to the shared memory. 16 pull-up resistors must be connected on the data bus. mbl = 0, the shared memory bus is at high impedance between two memory cycles and at low impedance during a write memory cycle. several multi-hdlc s can be connected to the shared memory. one pull-up resistor is recom- mended on each wire (control bus, address bus, data bus). sbv : six bit validation (a, e, s1/s4 bits). global validation for 16 channels (upstream and down- stream). sbv=1, in reception, the six bit word (a, e, s1/s4) located in the same timeslot as d channel can be received from any input timeslot; when this word is received identical twice consecutive- ly, it is stored in the external shared memory and an interrupt is generated if not masked (like the reception of primitive from c/i channel). sixteen independent detections are performed if the contents of any input timeslot is switched in the timeslot 4n+3 of two gci multiplexes (corresponding to dout4 and dout5) with (0 n 7). only the contents of d channel will be transmitted from input timeslot to gci multiplexes. in transmission a six bit word (a, e, s1/s4) can be transmitted continuously to any output times- lot via the tcir. this word (a, e, s1/s4) is set instead of primitive (c1, c2, c3, c4) and a, e bits received from the timeslot 4n+3 of two gci multiplexes and the new contents of this timeslot 4n+3 must be switched on the selected output timeslot. sbv=0, the 16 six bit detections are not validated. bit15 bit8 bit7 bit0 lp3 del3 st(3)1 st(3)0 lp2 del2 st(2)1 st(2)0 lp1 del1 st(1)1 st(1)0 lp0 del0 st(0)1 st(0)0 after reset (0000) h . during the whole of cycle duration on the outside of cycle mbl bus write cycle read cycle 1 a, c l l l dl z z 0 a, c l l z dl z z
STLC5466 34/130 vi.4 - input multiplex configuration register 1 imcr1 (06) h n.b. if din4 and din5 are gci multiplexes: then st(4)1 = st(4)0 = 0 and st(5)1 = st(5)0 = 0 normally. vi.5 - output multiplex configuration register 0 omcr0 (08) h see definition in next paragraph. vi.6 - output multiplex configuration register 1 omcr1 (0a) h bit15 bit8 bit7 bit0 lp7 del7 st(7)1 st(7)0 lp6 del6 st(6)1 st(6)0 lp5 del5 st(5)1 st(5)0 lp4 del4 st(4)1 st(4)0 after reset (0000) h st(i)0 : step0 for each input multiplex(i) with (0 i 7), delayed or not. st(i)1 : step1 for each input multiplex(i) with (0 i 7), delayed or not. del(i) : delayed multiplex i(0 i 7). when imtd = 0 (bit of smcr), del = 1 is not taken into account by the circuit. if tdm is at 2048 kb/s,1/2 bit-time is 244 ns, if tdm is at 4096 kb/s,1/2 bit-time is 122 ns. lp (i) : loopback 0/7 lpi = 1, output multiplex(i) is put instead of input multiplex(i) with (0 i 7). loopback is trans- parent or not in accordance with omvi (bit of output multiplex configuration register). lpi = 0, normal case, input multiplex(i) with (0 i 7) is taken into account. bit15 bit8 bit7 bit0 omv3 del3 st(3)1 st(3)0 omv2 del2 st(2)1 st(2)0 omv1 del1 st(1)1 st(1)0 omv0 del0 st(0)1 st(0)0 after reset (0000) h bit15 bit8 bit7 bit0 omv7 del7 st(7)1 st(7)0 omv6 del6 st(6)1 st(6)0 omv5 del5 st(5)1 st(5)0 omv4 del4 st(4)1 st(4)0 after reset (0000) h st(i)0 : step0 for each output multiplex(i) with (0 i 7), delayed or not. st(i)1 : step1 for each output multiplex(i) with (0 i 7), delayed or not. . del (i) st (i) 1 st (i) 0 step for each input multiplex 0/7 delayed or not x 0 0 each received bit is sampled at 3/4 bit-time without delay (tdm at 2 mb/s).first bit of the frame is defined by frame synchronization signal. 1 0 1 each received bit is sampled with 1/2 bit-time delay 1 1 0 each received bit is sampled with 1 bit-time delay 1 1 1 each received bit is sampled with 2 bit-time delay 0 0 1 each received bit is sampled with 1/2 bit-time advance 0 1 0 each received bit is sampled with 1 bit-time advance 0 1 1 each received bit is sampled with 2 bit-time advance
35/130 STLC5466 n.b. if dout4 and dout5 are gci multiplexes: then st(4)1 = st(4)0 = 0 and st(5)1 = st(5)0 = 0 normally. vi.7 - switching matrix configuration register smcr (0c) h del(i); : delayed multiplex(i) with (0 i 7). when imtd = 0 (bit of smcr), del = 0 is not taken into account by the circuit. if tdm is at 2048 kb/s,1/2 bit-time is 244 ns if tdm is at 4096 kb/s,1/2 bit-time is 122 ns omv (i) : output multiplex validated 0/7 omvi =1, condition to have dout(i) pin active (0 i 7). omvi =0, dout(i) pin is high impedance continuously (0 i 7). bit15 bit8 bit7 bit0 sw1 sw0 m1 m0 dr64 dr44 dr24 dr04 aisd me sgc sav sgv ts1 ts0 imtd after reset (0000) h imtd : increased minimum throughput delay when si = 0 (bit of cmdr, variable delay mode): imtd = 1, the minimum delay through the matrix memory is three time slots whatever the se- lected tdm output. imtd = 0, the minimum delay through the matrix memory is two time slots whatever the select- ed tdm output. in this case the input tdms cannot be delayed versus the frame synchroni- zation (use of imcr is limited) and the output tdms cannot be advanced versus the frame synchronization (use of omcr is limited). ts0 : tristate 0 ts0 = 1, the dout0/3 and dout6/7 pins are tristate: 0 is at low impedance, 1 is at low impedance and the third state is high impedance. ts0 = 0, the dout0/3 and dout6/7 pins are open drain: 0 is at low impedance, 1 is at high impedance. ts1 : tristate 1 ts1 = 1, the dout4/5 pins are tristate: 0 is at low impedance, 1 is at low impedance and the third state is high impedance. ts1 = 0, the dout4/5 pins are open drain: 0 is at low impedance, 1 is at high impedance. sgv : pseudo random sequence generator validated sgv = 1,prs generator is validated.the pseudo random sequence is transmitted during the related time slot(s). sgv = 0, prs generator is reset.0 are transmitted during the related time slot. del (i) st (i) 1 st (i) 0 step for each output multiplex 0/7 delayed or not x 0 0 each bit is transmitted on the rising edge of the double clock without delay. bit0 is defined by frame synchronization signal. 1 0 1 each bit is transmitted with 1/2 bit-time delay. 1 1 0 each bit is transmitted with 1 bit-time delay. 1 1 1 each bit is transmitted with 2 bit-time delay 0 0 1 each bit is transmitted with 1/2 bit-time advance. 0 1 0 each bit is transmitted with 1 bit-time advance. 0 1 1 each bit is transmitted with 2 bit-time advance
STLC5466 36/130 sav : pseudo random sequence analyser validated sav = 1, prs analyser is validated. sav = 0, prs analyser is reset. sgc : pseudo random sequence generator corrupted when sgc bit goes from 0 to 1, one bit of sequence transmitted is corrupted. when the corrupted bit has been transmitted, sgc bit goes from 1 to 0 automatically. me : message enable me = 1 the contents of connection memory is output on dout0/7 continuously. me = 0 the contents of connection memory acts as an address for the data memory. aisd : alarm indication signal detection. aisd=1, the alarm indication signal detection is validated. sixteen independent detections are performed for sixteen hyperchannels. the contents of any input hyperchannel (b1, b2) switched (in transparent mode or not) on gci channels is ana- lysed independently. for each gci channel, the 16 bits of b1and b2 channels are checked together; when all one has been detected during 30 milliseconds, a status is stored in the command/ indicate inter- rupt queue and an interrupt is generated if not masked (like the reception of primitive from gci multiplexes). aisd=0, the alarm indication signal detection for 16 hyperchannels is not validated. dr04 : data rate of tdm0 is at 4mb/s (case: m1=m0=0). dr04 = 1, the signal received from din0 pin and the signal delivered by dout0 pin are at 4mb/ s. din1 pin and dout1 pin are ignored. the time division multiplex 0 is constituted by 64 contiguous timeslots numbered from 0 to 63. dr04 = 0, the signals received from din0/1 pins and the signals delivered by dout0/1 pins are at 2mb/s. dr24 : data rate of tdm2 is at 4mb/s (case: m1=m0=0). dr24 = 1, the signal received from din2 pin and the signal delivered by dout2 pin are at 4mb/ s. din3 pin and dout3 pin are ignored. the time division multiplex 2 is constituted by contiguous 64 timeslots numbered from 0 to 63. dr24 = 0, the signals received from din2/3 pins and the signals delivered by dout2/3 pins are at 2mb/s. dr44 : data rate of tdm4 is at 4mb/s (case: m1=m0=0). dr44 = 1, the signal received from din4 pin and the signal delivered by dout4 pin are at 4mb/ s. din5 pin and dout5 pin are ignored. tdm4/5 cannot be gci multiplexes. the time division multiplex 4 is constituted by 64 contiguous timeslots numbered from 0 to 63. dr44 = 0, the signals received from din4/5 pins and the signals delivered by dout4/5 pins are at 2mb/s. dr64 : data rate of tdm6 is at 4mb/s (case: m1=m0=0). . dr64 = 1, the signal received from din6 pin and the signal delivered by dout6 pin are at 4mb/ s. din7 pin and dout7 pin are ignored. the switching matrix cannot be used to switch the channels to/from the hdlc controllers but the rx hdlc controller can be connected to din8 and the tx hdlc controller can be con- nected to cb pin. the time division multiplex 6 is constituted by 64 contiguous timeslots numbered from0 to 63. dr64 = 0, the signals received from din6/7 pins and the signals delivered by dout6/7 pins are at 2m b/s.
37/130 STLC5466 vi.8 - connection memory data register cmdr (0e) h this 16 bit register is constituted by two 8 bit registers: source register (srcr) and control register (ctlr). source register (srcr) this register defines the source when this source is located on an input time division multiplex itdmp: when d channels are multiplexed, see s0/s1 definition and tables here after. m1/0 : data rate of tdm0/8; these two bits indicate the data rate of height time division multiplexes tdm0/7 relative to din0/7 and dout0/7. the table below shows the different data rates with the clock frequency defined by hcl bit (general configuration register). n.b. the data rate of the time division multiplex relative to din8, cb and echo pins are at 2048 kbit/s or1536 kbit/s depending on m1/0 only. sw0 : switching at 32 kbit/s for the tdm0 (din0/dout0) sw0=1, din0 can receive 64 channels at 32 kbit/s. din2/dout2 are not available. din2 is used to receive internally tdm0 (din0) after 4 bit shifting dout2 is used to multiplex internally tdm2 and tdm4. sw0=0, din0 receives 32 (or 24) channels at 64 kbit/s or 64 channels at 64 kbit/s depending on dr04 bit and clocka/b. sw1 : switching at 32 kbit/s for the tdm1 (din1/dout1) sw1=1, din1 can receive 64 channels at 32 kbit/s. din3/dout3 are not available. din3 is used to receive internally tdm1(din1) after 4 bit shifting dout3 is used to multiplex internally tdm3 and tdm5. sw1=0, din1 receives 32 (or 24) channels at 64 kbit/s or 64 channels at 64 kbit/s depending on dr04 bit and clocka/b. control register (ctlr) source register (srcr) bit15 bit8 bit7 bit0 scr ps prsa s1 s0 otsv loop si im2 im1 im0 its 4 its 3 its 2 its 1 its 0 after reset (0000) h its 0/4 : input time slot 0/4 define itsx with: 0 x 31; im0/2 : input time division multiplex 0/2 define itdmp with: 0 p 7. m1 m0 data rate of tdm0/7 in kbit/s clocka/b signal frequency hcl=0 hcl=1 0 0 2048 (or 4096 in accordance with dr0x4) 4096 khz 8192 khz 0 1 1536 (or 3072 in accordance with dr0x4) 3072 khz 6144khz 1 0 reserved 1 1 reserved
STLC5466 38/130 control register (ctlr) defines each output time slot otsy of each output time division multi- plex otdmq: si : sequence integrity si = 1, the delay is always: (31 - itsx) + 32 + otsy (constant delay). si = 0, the delay is minimum to pass through the data memory (variable delay). loop: loopback per channel relevant if two connections has been established (bidirectional or not). loop = 1, otsy, otdmq is taken into account instead of itsy, itdmq. otsv = 1, transparent mode loopback. otsv = 0, not transparent mode loopback. otsv : output time slot validated otsv = 1, otsy otdmq is enabled. otsv = 0, otsy otdmq is high impedance. (otsy: output time slot with 0 y 31; otdmq: output time division multiplex with 0 q 7). s1/s0 : source s1 s0 source for each timeslot of dout0/7 0 0 data memory (normal case) 0 1 connection memory 1 0 d channels from/to gci multiplexes (see note and table hereafter) 1 1 pseudo random sequence generator delivers sequences. hyperchannel at n x 64 kb/s is possible. note: ? connection when the source of d channels is selected (gci channels defined by its 1/0) and when the destination is selected (output timeslot defined by ots 0/4; output tdm defined by om 0/2) the upstream connection is set up; the downstream connection (reverse direction tdm to gci) is set up automatically if its 2 bit is at 1. so bid, bit of cmar must be written at0. ?release remember: write s1=1, s0=0 and its 2 bit = 0 to release the downstream connection; the up- stream connection is released when the source changes.
39/130 STLC5466 table: switching at 16 kb/s when its3=0 s1 s0 its3 its2 itsi its 0 upstream source: d channels of one gci channel destination: two bits of one tdm downstream source: two bits of one tdm destination: d channels of one gci channel 10 0 1 00 the contents of d channels of gci 0 /3 of multiplex din4 are transferred into the output times- lot of one tdm defined by the destination register (cmar). d channel of gci 0 in bit 1/2 d channel of gci 1 in bit 3/4 d channel of gci 2 in bit 5/6 d channel of gci 3 in bit 7/8 the contents of the input times lot (same number as the number of the output timeslot) is transferred in d channel of gci 0/3 of multiplex dout4 bit 1/2 in d channel of gci 0 bit 3/4 in d channel of gci 1 bit 5/6 in d channel of gci 2 bit 7/8 in d channel of gci 3 01 the contents of d channels of gci 4/7 of multiplex din4 are transferred into the output times- lot of one tdm defined by the destination register (cmar). d channel of gci 4 in bit 1/2 d channel of gci 5 in bit 3/4 d channel of gci 6 in bit 5/6 d channel of gci 7 in bit 7/8 the contents of the input times lot (same number as the number of the output timeslot) is transferred in d channel of gci 4/7 of multiplex dout4. bit 1/2 in d channel of gci 4 bit 3/4 in d channel of gci 5 bit 5/6 in d channel of gci 6 bit 7/8 in d channel of gci 7 10 the contents of d channels of gci 0 /3 of multiplex din5 are transferred into the output times- lot of one tdm defined by the destination register (cmar). d channel of gci 0 in bit 1/2 d channel of gci 1 in bit 3/4 d channel of gci 2 in bit 5/6 d channel of gci 3 in bit 7/8 the contents of the input times lot (same number as the number of the output timeslot) is transferred in d channel of gci 0/3 of multiplex dout5. bit 1/2 in d channel of gci 0 bit 3/4 in d channel of gci 1 bit 5/6 in d channel of gci 2 bit 7/8 in d channel of gci 3 11 the contents of d channels of gci 4/7 of multiplex din5 are transferred into the output times- lot of one tdm defined by the destination register (cmar). d channel of gci 4 in bit 1/2 d channel of gci 5 in bit 3/4 d channel of gci 6 in bit 5/6 d channel of gci 7 in bit 7/8 the contents of the input times- lot (same number as the number of the output timeslot) is transferred in d channel of gci 4/7 of multiplex dout5. bit 1/2 in d channel of gci 4 bit 3/4 in d channel of gci 5 bit 5/6 in d channel of gci 6 bit 7/8 in d channel of gci 7
STLC5466 40/130 table: switching at 16 kb/s when its3=1 s1 s0 its3 its2 itsi its 0 upstream source: d channels of one gci channel destination: two bits of one tdm downstream source: two bits of one tdm destination: d channels of one gci channel 10 1 1 00 the contents of d channels of gci 0 /3 of multiplex din4 are transferred into the output times- lot of one tdm defined by the destination register (cmar). d channel of gci 0 in bit 7/8 d channel of gci 1 in bit 5/6 d channel of gci 2 in bit 3/4 d channel of gci 3 in bit 1/2 the contents of the input times lot (same number as the number of the output timeslot) is transferred in d channel of gci 0/3 of multiplex dout4 bit 7/8 in d channel of gci 0 bit 5/6 in d channel of gci 1 bit 3/4 in d channel of gci 2 bit 1/2 in d channel of gci 3 01 the contents of d channels of gci 4/7 of multiplex din4 are transferred into the output times- lot of one tdm defined by the destination register (cmar). d channel of gci 4 in bit 7/8 d channel of gci 5 in bit 5/6 d channel of gci 6 in bit 3/4 d channel of gci 7 in bit 1/2 the contents of the input times lot (same number as the number of the output timeslot) is transferred in d channel of gci 4/7 of multiplex dout4. bit 7/8 in d channel of gci 4 bit 5/6 in d channel of gci 5 bit 3/4 in d channel of gci 6 bit 1/2 in d channel of gci 7 10 the contents of d channels of gci 0 /3 of multiplex din5 are transferred into the output times- lot of one tdm defined by the destination register (cmar). d channel of gci 0 in bit 7/8 d channel of gci 1 in bit 5/6 d channel of gci 2 in bit 3/4 d channel of gci 3 in bit 1/2 the contents of the input times lot (same number as the number of the output timeslot) is transferred in d channel of gci 0/3 of multiplex dout5. bit 7/8 in d channel of gci 0 bit 5/6 in d channel of gci 1 bit 3/4 in d channel of gci 2 bit 1/2 in d channel of gci 3 11 the contents of d channels of gci 4/7 of multiplex din5 are transferred into the output times- lot of one tdm defined by the destination register (cmar). d channel of gci 4 in bit 7/8 d channel of gci 5 in bit 5/6 d channel of gci 6 in bit 3/4 d channel of gci 7 in bit 1/2 the contents of the input times- lot (same number as the number of the output timeslot) is transferred in d channel of gci 4/7 of multiplex dout5. bit 7/8 in d channel of gci 4 bit 5/6 in d channel of gci 5 bit 3/4 in d channel of gci 6 bit 1/2 in d channel of gci 7 prsa :s pseudo random sequence analyser if prsa = 1, prs analyser is enabled during otsy otdmq and receives data: s0 = 0, data comes from data memory. s0 = 1 and s1 = 1, data comes from prs generator (test mode). if prsa = 0, prs analyser is disabled during otsy otdmq.
41/130 STLC5466 vi.9 - connection memory address register cmar (10) h this 16 bit register is constituted by two registers: destination register (dstr) and access mode register (amr) respectively 8 bits and 6 bits. destination register (dstr) only when dstr is written by the microprocessor, a memory access is launched . dstr has two use modes depending on cm (bit of cmar). cm = 1, access to connection memory (read or write); when cm = 1, ots 0/4 and om 0/2 bits are defined hereafter: see table hereafter when dr04, dr24, dr44 and/or dr64 are at 1; these bits of smcr define the tdms at 4 mbit/s. ps : programmable synchronization if ps = 1, programmable synchronization signal pin is at 1 during the bit time defined by otsy and otdmq. for otsy and otdmq with y = q = 0, pss pin is at 1 during the first bit of the frame defi ned by the frame synchronization signal (fs). if ps = 0, pss pin is at 0 during the bit time defined by otsy and otdmq. scr : scrambler/ descrambler scr=1, the scrambler or the descrambler are enabled. both of them are located after the switch- ing matrix. the scrambler is enabled when the output timeslot defined by the destination register (dstr) is an output timeslot belonging to any tdm except the two gci multiplexes; the contents of this out- put timeslot will be scrambled in accordance with the iut-t v.29 rec. the descrambler is enabled when the output timeslot defined by the destination register (dstr) is an output timeslot belonging to the two gci multiplexes except any tdm; the contents of this output timeslot is descrambled in accordance with the iut-t v.29 rec. only 32 timeslots of 256 can be scrambled or/and descrambled: gci side, only b1 and b2 can be selected in each gci channel (16 gci channels are available: 8 per gci multiplex). *tdm side, it is forbidden to select a given timeslot more than once when several tdms are se- lected. scr=0, the scrambler or the descrambler are disabled; the contents of output timeslots are not modified. access mode register (amr) destination register (dstr) bit15 bit8 bit7 bit0 nu nu tc cacl cac bid cm read om2 om1 om0 ots4 ots3 ots2 ots1 ots0 after reset (0800) h ots 0/4 : output time slot 0/4 define otsy with: 0 y 31; om0/2 : output time division multiplex 0/2 define otdmq with: 0 q 7.
STLC5466 42/130 C the im2/1 bits of source register (srcr of cmdr) indicate the din pin number and the om2/1 bits of destination register (dstr of cmar) indicate the dout pin number C the its4/0 and im0 bits of source register (srcr of cmdr) indicate the input timeslot number. (im0 bit is the least significant bit; it indicates either even timeslot or odd timeslot. C the ots4/0 and om0 bits of destination register (dstr of cmar) indicate the output timeslot number. (om0 bit is the least significant bit; it indicates either even timeslot or odd timeslot. ? nota bene: clock a/b is at 4 or at 8 mhz in accordance with hcl bit of general configuration register gcr (02). C hcl=1, bit clock frequency is at 8 192 khz. for a tdm at 4 mbit/s or 2mbit/s, each received bit is sampled at 3/4 bit-time. im2 (bit7) im1 (bit6) din pin om2 (bit7) om1 (bit6) dout pin 0 0 din0 0 0 dout0 0 1 din2 0 1 dout2 1 0 din4 1 0 dout4 1 1 din6 1 1 dout6 its4 (bit4) its3 (bit3) its2 (bit2) its1 (bit1) its0 (bit0) im0 (bit5) input timeslot number 0000 0 0 0 0000 0 1 1 0000 1 0 2 0000 1 1 3 0001 0 0 4 0001 0 1 5 1111 1 1 63 ots4 (bit4) ots3 (bit3) ots2 (bit2) ots1 (bit1) ots0 (bit0) om0 (bit5) output timeslot number 0000 0 0 0 0000 0 1 1 0000 1 0 2 0000 1 1 3 0001 0 0 4 0001 0 1 5 1111 1 1 63
43/130 STLC5466 C hcl=0, bit clock frequency is at 4 096 khz for a tdm at 4 mbit/s, each received bit is sampled at half bit-time (at 4 mbit/s, bit-time=244ns). for a tdm at 2 mbit/s, each received bit is sampled at 3/4 bit-time (at 2 mbit/s, bit-time=488ns). ? remarks: om0 , bit5 of dstr indicates either even tdm or odd tdm if tdm at 2 mb/s. om0 , bit5 of dstr indicates either even output timeslot or odd output timeslot if tdm at 4 mb/s. im0 , bit5 of srcr indicates either even tdm or odd tdm if tdm at 2 mb/s. im0 , bit5 of srcr indicates either even input timeslot or odd input timeslot if tdm at 4 mb/s.
STLC5466 44/130 access mode register (amr) read : read memory read = 1, read connection memory (or data memory in accordance with cm). read = 0, write connection memory. cm : connection memory cm = 1, write or read connection memory in accordance with read. cm = 0, read only data memory (read = 0 has no effect). n.b. after software reset (bit 2 of idcr register) or pin reset the automate of the connection memory is launched. this automate initializes the connection memory within 250 microsec- onds at the most. this automate is stopped when the microprocessor writes (0200h) in cmar register (cm =1). bid : bidirectionnal connection. bid = 1; two connections are set up: ? itsx itdmp ------> otsy otdmq (loop of cmdr register is taken into account) and ? itsy itdmq ------> otsx otdmp (loop of cmdr register is not taken into account). bid = 0; one connection is set up: ? itsx itdmp ------> otsy otdmq only. cac : cyclical access cac = 1 (bid is ignored) if write connection memory, an automatic data write from connection memory data register (cmdr) up to 256 locations of connection memory occurs. the first address is indicated by the register dstr, the last is (ff)h. if read connection memory, an automatic transfer of data from the location indicated by the register (dstr) into connection memory data register (cmdr) after reading by the micro- processor occurs. the last location is (ff)h. cac = 0, write and read connection memory in the normal way. ? n.b. after software reset (bit 2 of idcr register) or pin reset an automate is working to reset the con- nection memory (all 0). the automate is stopped when the microprocessor writes taar register with cac= 0. cacl : cyclical access limited cacl = 1(bid is ignored) if write connection memory, an automatic data write from connection memory data register (cmdr) up to 32 locations of connection memory occurs. the first location is indicated by ots 0/4bits of the register (dstr) related to otdmq as defined by om0/2 occurs. the last location is q +1 f(h). if read connection memory, an automatic transfer of data from connection memory into con- nection memory data register (cmdr) after reading this last by the microprocessor oc- curs.the first location is indicated by ots 0/4 bits of the register (dstr) related to otdmq as defined by om0/2. the last location is q +1 f(h). cacl = 0, write and read connection memory in the normal way. tc : transparent connection tc = 1, (bid is ignored) if read = 0: cac = 0 and cacl = 0. the dstr bits are taken into account instead of srcr bits. srcr bits are ignored (destination and source are identical). the contents of input time slot i - input multiplex j is switched into output time slot i - output multiplex j. cac = 0 and cacl = 1. up to 32 transparent connections are set up. cac = 1 and cacl = 0. up to 256 transparent connections are set up. tc = 0, write and read connection memory in accordance with bid.
45/130 STLC5466 vi.10 - sequence fault counter register sfcr (12) h when this register is read by the microprocessor, this register is reset (0000)h. ? nb. as the sfcr is reset after reading, a 8-bit microprocessor must read the lsb that will represent the number of faults between 0 and 255. to avoid overflow escape notice, it is necessary to start counting at ff00h, by writing this value in sfcr before launching prsa. if there are more than ffh errors, the sfco interrupt bit (see interrupt register ir -38h address) will signal that the fault count register has reached the value ffffh (because of the number of faults exeeded 255). vi.11 - time slot assigner address register 1 taar1 (14) h ? n.b. after software reset (bit 2 of idcr register) or pin reset the automate above mentioned is working. the automate is stopped when the microprocessor writes taar register with hdi = 0. vi.12 - time slot assigner data register 1 tadr1 (16) h bit15 bit8 bit7 bit0 f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 after reset (0000) h f0/15 : fault0/15 number of faults detected by the pseudo random sequence analyser if the analyser has been validated and has recovered the receive sequence. when the fault counter register reaches (ffff)h it stays at its maximum value. bit15 bit8 bit7 bit0 ts4 ts3 ts2 ts1 ts0 read nu hdi r e s e r v e d after reset (0100) h read : read memory read = 1, read time slot assigner memory 1. read = 0, write time slot assigner memory 1. ts0/4 : time slots0/4 these five bits define one of 32 time slots in which a channel is set-up or not. hdi : hdlc1 init hdi = 1, tsa1 memory, tx hdlc1, tx dma1, rx hdlc1, rx dma1 and gci controllers are reset within 250 microseconds at the most. an automate writes data from time slot assigner data register1 (tadr1) (except ch0/4 bits) into each tsa memory location. if the microproc- essor reads time slot assigner memory 1 after hdlc init, ch0/4 bits of time slot assigner data register are identical to ts0/4 bits of time slot assigner address register 1. hdi = 0, normal state. bit15 bit8 bit7 bit0 v11 v10 v9 v8 v7 v6 v5 v4 v3 v2 v1 ch4 ch3 ch2 ch1 ch0 after reset (0000) h ch0/4 : channel0/4 these five bits define one of 32 channels associated to time slot defined by the previous register 1(taar1). v1/8 : validation the logical channel chx is constituted by each subchannel 1 to 8 and validated by v1/8 bit at 1 re- spectively. v1 to v8 are at 0: the subchannels are ignored. v1 corresponds to the first bit received during the current time slot. v1 at 1: the first bit of the current time slot is taken into account in reception and in transmission the first bit transmitted is taken into account. v8 at 1: the last bit of the current time slot is taken into account in reception the last bit received and in transmission the last bit transmitted in transmission.
STLC5466 46/130 vi.13 - hdlc transmit command register 1 htcr1 (18) h v9 : validation subchannel v 9 = 1, each v1/8 bit is taken into account once every 250 m s. in transmit direction , data is transmitted consecutively during the time slot of the current frame and during the same time slot of the next frame.id est.: the same data is transmitted in two con- secutive frames. in receive direction , hdlc controller fetches data during the time slot of the current frame and ignores data during the same time slot of the next frame. v 9 = 0, each v1/8 bit is taken into account once every 125 m s. v10 : direct mhdlc access if v10 = 1, the rx hdlc controller 1 receives data issued from din8 input during the current time slot (bits validated by v1/8) and dout6 output transmits data issued from the tx hdlc controller. if v10 = 0, the rx hdlc controller1 receives data issued from the matrix output 7 during the current time slot; dout6 output delivers data issued from the matrix output 6 during the same current time slot. n.b: if d7 = 1, bit of general configuration register gcr1 the tx hdlc controller1 is connect- ed to matrix input 7 continuously so the hdlc frames can be sent to any dout (i.e. dout0 to dout7). v11 : validation of cb pin this bit is not taken into account if csma = 1 (hdlc transmit command register). if csma = 0: v11 = 1, contention 1 bus pin is validated and echo 1 pin (which is an input) is not taken into account. v11 = 0, contention bus pin is high impedance during the current time slot (this pin is an open drain output). bit15 bit8 bit7 bit0 ch4 ch3 ch2 ch1 ch0 read nu cf pen csma ncrc f p1 p0 c1 c0 after reset (0000) h read : read command memory read = 1, read command memory. read = 0, write command memory. ch0/4 : these five bits define one of 32 channels. c1/c0 : command bits c1 c0 command bits written by the microprocessor 0 0 abort; if this command occurs during the current frame, hdlc controller transmits seven 1 immediately, afterwards hdlc controller transmits 1 or flag in accordance with f bit, generates an interrupt and waits new command such as start or continue. if this command occurs after transmitting a frame, hdlc controller generates an interrupt and waits a new command such as start or continue. 0 1 start; tx dma controller is now going to transfer first frame from buffer related to initial de- scriptor. the initial descriptor address is provided by the initiate block located in external memory. 1 0 continue; tx dma controller is now going to transfer next frame from buffer related to next descriptor. the next descriptor address is provided by the previous descriptor from which the related frame had been already transmitted. 1 1 halt; after transmitting frame, hdlc controller transmits 1 or flag in accordance with f bit, generates an interrupt and is waiting new command such as start or continue.
47/130 STLC5466 c1/c0 : status bits p0/1 : protocol bits f:flag f = 1; flags are transmitted between closing flag of current frame and opening flag of next frame. f = 0; 1 are transmitted between closing flag of current frame and opening flag of next frame. ncrc : crc not transmitted ncrc = 1, the crc is not transmitted at the end of the frame. ncrc = 0, the crc is transmitted at the end of the frame. csma : carrier sense multiple access with contention resolution csma = 1, cb1 output and the echo bit are taken into account during this channel transmission by the txhdlc. csma = 0, cb output and the echo bit are defined by v11, bit of time slot assigner data reg- ister tadr1 (16) h . pen : csma penalty significant if csma = 1 pen = 1, the penalty value is 1; a transmitter which has transmitted a frame correctly will count (pri +1) logic one received from echo pin before transmitting next frame. (pri, priority class 8 or 10 given by the buffer descriptor related to the frame. pen = 0, the penalty value is 2; a transmitter which has transmitted a frame correctly will count (pri +2) logic one received from echo pin before transmitting next frame. (pri, priority class 8 or 10 given by the transmit descriptor related to the frame). cf : common flag cf = 1, the closing flag of previous frame and opening flag of next frame are identical if the next frame is ready to be transmitted. cf = 0, the closing flag of previous frame and opening flag of next frame are distinct. c1 c0 status bits read by the microprocessor 0 0 abort; the microprocessor has written abort or the transmitted frame has been aborted by the hdlc controller and it waits new command such as start or continue. 0 1 start; the microprocessor has written start.the hdlc controller has not taken into ac- count the command yet. 1 0 continue; the hdlc controller has taken into account the command start. tx dma controller is transferring frames. 1 1 continue; tx dma controller is now going to transfer next frame from buffer related to next descriptor. the next descriptor address is provided by the previous descriptor from which the related frame had been already transmitted. p1 p0 transmission mode 00hdlc 0 1 transparent mode 1 (one byte per timeslot); the fill character defined in fcr register is taken into account. 1 0 transparent mode 2 (one byte per timeslot); the fill character defined in fcr register is not taken into account. 1 1 reserved
STLC5466 48/130 vi.14 - hdlc receive command register 1 hrcr1 (1a) h bit15 bit8 bit7 bit0 ch4 ch3 ch2 ch1 ch0 read ar21 ar20 ar11 ar10 crc fm p1 p0 c1 c0 after reset (0000) h read : read command memory read = 1, read command memory. read = 0, write command memory. ch0/4 : these five bits define one of 32 channels. c1/c0 : command bits c1/c0 : status bits p0/1 : protocol bits c1 c0 command bits written by the microprocessor 0 0 abort; if this command occurs during receiving a current frame, hdlc controller stops the reception, generates an interrupt and waits new command such as start or continue. if this command occurs after receiving a frame, hdlc controller generates an interrupt and waits a new command such as start or continue. 0 1 start; rx dma controller is now going to transfer first frame into buffer related to the initial descriptor. the initial descriptor address is provided by the initiate block located in external memory. 1 0 continue; rx dma controller is now going to transfer next frame into buffer related to next descriptor. the next descriptor address is provided by the previous descriptor from which the related frame had been already received. 1 1 halt; after receiving a frame, hdlc controller stops the reception, generates an interrupt and waits a new command such as start or continue. c1 c0 status bits read by the microprocessor 0 0 abort; the received current frame has been aborted (seven 1 at least have been received) or the microprocessor has written abort. the hdlc controller waits a new command such as start or continue 0 1 start; the microprocessor has written start.the hdlc controller has not taken into ac- count the command yet. 1 0 continue; rx dma controller is transferring frames 1 1 halt; hdlc controller stops the reception, generates an interrupt and waits a new com- mand such as start or continue. p1 p0 transmission mode 00hdlc 0 1 transparent mode 1 (one byte per timeslot); the fill character defined in fcr register is taken into account. 1 0 transparent mode 2 (one byte per timeslot); the fill character defined in fcr register is not taken into account. 1 1 reserved
49/130 STLC5466 fm : flag monitoring this bit is a status bit read by the microprocessor. fm=1: hdlc controller is receiving a frame or hdlc controller has just received one flag. fm is put to 0 by the microprocessor. crc : crc stored in external memory crc = 1, the crc is stored at the end of the frame in external memory. crc = 0, the crc is not stored into external memory. ar10 : address recognition10 ar10 = 1, first byte after opening flag of received frame is compared to af0/7 bits of afrdr. if the first byte received and af0/7 bits are not identical the frame is ignored. ar10 = 0, first byte after opening flag of received frame is not compared to af0/7 bits of afrdr register. ar11 : address recognition 11 ar11 = 1, first byte after opening flag of received frame is compared to all 1s.if the first byte received is not all 1s the frame is ignored. ar11 = 0, first byte after opening flag of received frame is not compared to all 1s. ar20 : address recognition 20 ar20 = 1, second byte after opening flag of received frame is compared to af8/15 bits of afrdr register. if the second byte received and af8/15 bits are not identical the frame is ig- nored. ar20 = 0, second byte after opening flag of received frame is not compared to af8/15 bits of afrdr register. ar21 : address recognition 21 ar21 = 1, second byte after opening flag of received frame is compared to all 1s. if the sec- ond byte received is not all 1s the frame is ignored. ar21 = 0, second byte after opening flag of received frame is not compared to all 1s. second byte first byte conditions to receive a frame ar21 ar20 ar11 ar10 0 0 0 0 each frame is received without condition. 0 0 0 1 only value of the first received byte must be equal to that of af0/7 bits. 0 0 1 0 only value of the first received byte must be equal to all 1s. 0 0 1 1 the value of the first received byte must be equal either to that of af0/7 or to all 1s. 0 1 0 0 only value of the second received byte must be equal to that of af8/15 bits. 0 1 0 1 the value of the first received byte must be equal to that of af0/7 bits and the value of the second received byte must be equal to that of af8/15 bits. 0 1 1 0 the value of first received byte is must be equal to all 1s and the value of sec- ond received byte must be equal to that of af8/15 bits. 0 1 1 1 the value of the first received byte must be equal either to that of af0/7 or to all 1s and the value of the second received byte must be equal to that of af8/15 bits. 1 0 0 0 only the value of the second received byte must be equal to all 1s. 1 0 0 1 the value of the first received byte must be equal to that of af0/7 bits and the value of the second received byte must be equal to all 1s.
STLC5466 50/130 vi.15 - address field recognition address register 1 afrar1 (1c) h the write operation is launched when afrar is written by the microprocessor. vi.16 - address field recognition data register 1 afrdr1 (1e) h 1 0 1 0 the value of the first received byte must be equal to all 1s and the value of the second received byte must be equal to 1 also. 1 0 1 1 the value of the first received byte must be equal either to that of af0/7 or to 1 and the value of the second received byte must be equal to all 1s. 1 1 0 0 the value of the second received byte must be equal either to that of af8/15 or to all 1s. 1 1 0 1 the value of the first received byte must be equal to that of af0/7 bits and the value of the second received byte must be equal either to that of af8/15 or to all 1s. 1 1 1 0 the value of the first received byte must be equal to 1 and the value of the sec- ond received byte must be equal either to that of af8/15 or to all 1s. 1 1 1 1 the value of the first received byte must be equal either to that of af0/7 or to 1 and the value of the second received byte must be equal either to that of af8/15 or to all 1s. bit15 bit8 bit7 bit0 ch4 ch3 ch2 ch1 cho read amm nu r e s e r v e d after reset (0000) h amm : access to mask memory amm=1, access to address field recognition mask memory. amm=0, access to address field recognition memory. read : read address field recognition memory read=1, read afr memory. read=0, write afr memory. ch0/4 : these five bits define one of 32 channels in reception bit15 bit8 bit7 bit0 af15/ afm15 af14/ afm14 af13/ afm13 af12/ afm12 af11/ afm11 af10/ afm10 af9/ afm9 af8/ afm8 af7/ afm7 af6/ afm6 af5/ afm5 af4/ afm4 af3/ afm3 af2/ afm2 af1/ afm1 af0/ afm0 after reset (0000) h af0/15 : address field bits af0/7; first byte received; af8/15: second byte received. these two bytes are stored into address field recognition memory when afrar1 is written by the microprocessor. afm0/ 15 : address field bit mask0/15 if amm=1 (amm bit of afrar1) amf0/7. when ar10=1 (see hrcr1) each bit of the first received byte is compared respectively to afx bit if afmx=0. in case of mismatching, the received frame is ignored. if afmx=1, no comparison between afx and the corresponding received bit. amf8/15. when ar20=1 (see hrcr1) each bit of the second received byte is compared respectively to afy bit if afmy=0. in case of mismatching, the received frame is ignored. if afmy=1, no comparison be- tween afy and the corresponding received bit. these two bytes are stored into address field recognition mask memory when afrar 1 is written by the microprocessor (amm=1). second byte first byte conditions to receive a frame ar21 ar20 ar11 ar10
51/130 STLC5466 vi.17 - fill character register 1 fcr1 (20) h vi.18 - gci channels definition register 0 gcir0 (22) h the definitions of x and y indices are the same for gcir0, gcir1, gcir2, gcir3: C 0 x 7, 1 of 8 gci channels belonging to the same multiplex tdm4 or tdm5 C y = 0, tdm4 is selected C y = 1, tdm5 is selected. vi.19 - gci channels definition register 1 gcir1 (24) h for definition see gci channels definition register above. bit15 bit8 bit7 bit0 r e s e r v e d fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 after reset (0000) h fc0/7 : fill character (eight bits) in transparent mode m1, two messages are separated by fill characters and the de- tection of one fill character marks the end of a message. bit15 bit8 bit7 bit0 ana11 vci11 v*11 vm11 ana10 vci10 v*10 vm10 ana01 vci01 v*01 vm01 ana00 vci00 v*00 vm00 tdm5 tdm4 tdm5 tdm4 gci channel 1 gci channel 0 after reset (0000) h vmxy : validation of monitor channelx, multiplex y: when this bit is at 1, monitor channel xy is validated. when this bit is at 0, monitor channel xy is not validated. on line to reset (if necessary) one mon channel which had been selected previously vmxy must be put at 0 during 125 m s before reselecting this channel. deselecting one mon channel during 125 m s resets this mon channel. v*xy : validation of v star x, multiplex y when this bit is at 1, v star protocol is validated if vmxy=1. when this bit is at 0, gci monitor protocol is validated if vmxy=1. vcxy : validation of command/indicate channel x, multiplexy when this bit is at 1, command/indicate channel xy is validated. when this bit is at 0, command/indicate channel xy is not validated. it is necessary to let vcxy at 0 during 125 m s to initiate the command/indicate channel. anaxy : analog application when this bit is at 1, primitive has 6 bits if c/ixy is validated. when this bit is at 0, primitive has 4 bits if c/ixy is validated. bit15 bit8 bit7 bit0 ana31 vci31 v*31 vm31 ana30 vci30 v*30 vm30 ana21 vci21 v*21 vm21 ana20 vci20 v*20 vm20 tdm5 tdm4 tdm5 tdm4 gci channel 3 gci channel 4 after reset (0000) h
STLC5466 52/130 vi.20 - gci channels definition register 2 gcir2 (26) h for definition see gci channels definition register above. vi.21 - gci channels definition register 3 gcir3 (28) h for definition see gci channels definition register above. vi.22 - transmit command / indicate register tcir (2a) h when this register is written by the microprocessor, these different bits mean: bit15 bit8 bit7 bit0 ana51 vci51 v*51 vm51 ana50 vci50 v*50 vm50 ana41 vci41 v*41 vm41 ana40 vci40 v*40 vm40 tdm5 tdm4 tdm5 tdm4 gci channel 5 gci channel 6 after reset (0000) h bit15 bit8 bit7 bit0 ana71 vci71 v*71 vm71 ana70 vci70 v*70 vm70 ana61 vci61 v*61 vm61 ana60 vci60 v*60 vm60 tdm5 tdm4 tdm5 tdm4 gci channel 7 gci channel 8 after reset (0000) h bit15 bit8 bit7 bit0 d g0 ca2 ca1 ca0 read 0 0 nu nu c6/a c5/e c4/s1 c3s2 c2s3 c1s4 after reset (00ff) h read : read c/i memory read = 1, read c/i memory. read = 0, write c/i memory. ca 0/2 : transmit command/indicate memory address ca0/2: these bits define one of eight command/indicate channels. g0 : this bit defines one of two gci multiplexes. g0 = 0, tdm4 is selected. g0 = 1, tdm5 is selected. c6/1 : new primitive to be transmitted c6 is transmitted first if ana = 1. c4 is transmitted first if ana = 0. d : destination; this bit defines the destination of bit 0 to 5. d=0: the primitive c6 to c1 is transmitted directly into gci channel defined by g0 and ca 0/2 d=1: the 6 bit word a, e, s1, s2, s3, s4 is put instead of the six bits received latest during the timeslot 4n+3 (gci channel defined by g0 and ca 0/2) and transmitted into any selected out- put timeslot after switching. bit15 bit8 bit7 bit0 d=0g0 ca2ca1ca0read0 0 nunuc6c5c4c3c2c1 d=1 g0 ca2 ca1 ca0 read 0 0 a e s1 s2 s3 s4 c6/1 : new primitive to be transmitted to the selected gci channel (dout4 or dout5) a, e, s1 to s4 : new 6 bit word to be transmitted into any output timeslot.
53/130 STLC5466 the new primitive is taken into account by the transmitter after writing bits 8 to 15 (if 8bit microprocessor). transmit command/indicate register (after reading) when this register is read by the microprocessor, these different bits mean: vi.23 - transmit monitor address register tmar (2c) h when this register is written by the microprocessor, these different bits mean: bit15 bit8 bit7 bit0 d=0 g0 ca2 ca1 ca0 read nu nu pt1 pt0 c6 c5 c4 c3 c2 c1 d=1 g0 ca2 ca1 ca0 read nu nu pt1 pt0 a e s1 s2 s3 s4 read : read c/i memory read = 1, read c/i memory. read = 0, write c/i memory. ca 0/2 : transmit c/i address ca0/2: these bits define one of eight command/indicate channels. g0 : this bit defines one of two gci multiplexes. g0 = 0, tdm4 is selected. g0 = 1, tdm5 is selected. d : destination. this bit defines the destination of bits 0 to 5. d=0: the destination is a gci channel defined by g0 and ca0/2. d=1:the destination is any tdm (after switching). c6/1 : last primitive transmitted. case of d=0 a, e, s1 to s4 : 6 bit word transmitted. case of d=1. pt0/1 : status bits bit15 bit8 bit7 bit0 0 g0 ma2 ma1 ma0 read nu nu nu nu tiv fabt l nob 0 nu after reset (000f) h read : read mon memory read=1, read mon memory. read=0, write mon memory. ma 0/2 : transmit monitor address ma 0/2:these bits define one of eight monitor channel if validated. g0 : this bit defines one of two gci multiplexes. g0 = 0, tdm4 is selected. g0 = 1, tdm5 is selected. nob : number of byte to be transmitted nob = 1, one byte to transmit. nob = 0, two bytes to transmit. p1 p0 primitive status 0 0 primitive has not been transmitted yet. 0 1 primitive has been transmitted once. 1 0 primitive has been transmitted twice. 1 1 primitive has been transmitted three times or more.
STLC5466 54/130 if 8 bit microprocessor the data (tmdr register) is taken into account by the transmitter after writing bits 8 to 15 of this register. transmit monitor address register (after reading) when this register is read by the microprocessor, these different bits mean: vi.24 - transmit monitor data register tmdr (2e) h l : last byte l = 1, the word (or the byte) located in the transmit monitor data register (tmdr) is the last. l = 0, the word (or the byte) located in the transmit monitor data register (tmdr) is not the last. fabt : fabt = 1, the current message is aborted by the transmitter. tiv : timer interrupt is validated tiv = 1, time out alarm generates an interrupt when the timer has expired. tiv = 0, time out alarm is masked. bit15 bit8 bit7 bit0 0 g0 ma2 ma1 ma0 read nu nu nu nu to abt l nobt exe idle read, ma0/2, g0 have same definition as already described for the write register cycle. idle : when this bit is at 1, idle (all 1s) is transmitted during the channel validation. exe : executed when this status bit is at 1, the command written previously by the microprocessor has been executed and a new word can be stored in the transmit monitor data register (tmdr) by the microprocessor. when this bit is at 0, the command written previously by the microprocessor has not yet been executed. nobt : number of byte which has been transmitted. nobt = 1, the first byte is transmitting. nob t = 0, the second byte is transmitting, the first byte has been transmitted. l : last byte, this bit is the l bit which has been written by the microprocessor. abt : abort abt=1, the remote receiver has aborted the current message. to : time out one millisecond to = 1, the remote receiver has not acknowledged the byte which has been transmitted one millisecond ago. bit15 bit8 bit7 bit0 m18 m17 m16 m15 m14 m13 m12 m11 m08 m07 m06 m05 m04 m03 m02 m01 after reset (ffff) h m08/01 : first monitor byte to transmit. m08 bit is transmitted first. m18/11 : second monitor byte to transmit if nob = 0 (bit of tmar). m18 bit is transmitted first.
55/130 STLC5466 vi.25 - transmit monitor interrupt register tmir (30) h when the microprocessor read this register, this register is reset (0000) h. vi.26 - memory interface configuration register micr (32) h bit15 tdm5 bit8 bit7 tdm4 bit0 mi71 mi61 mi51 mi41 mi31 mi21 mi11 mi01 mi70 mi60 mi50 mi40 mi30 mi20 mi10 mi00 after reset (0000) h mixy : transmit monitor channel x interrupt, multiplex y with: 0 x 7, 1 of 8 gci channels belonging to the same multiplex tdm4 or tdm5 y = 0, gci channel belongs to the multiplex tdm4 and y = 1 to tdm5. mixy = 1 when: C a word has been transmitted and pre-acknowledged by the transmit monitor channel xy (in this case the transmit monitor data register (tmdr) is available to transmit a new word) or C the message has been aborted by the remote receive monitor channel or C the timer has reached one millisecond (in accordance with tiv bit of tmar) by im3 bit of imr. when mixy goes to 1, the interrupt mtx bit of ir is generated. interrupt mtx can be masked. bit15 bit8 bit7 bit0 p41 p40 p31 p30 p21 p20 p11 p10 nu nu nu nu nu nu nu ref after reset (0000) h ref : memory refresh ref=1, sdram refresh is validated ref=0, sdram refresh is not validated p1 e0/1 p2 e0/1 p3 e0/1 p4 e0/1 priority 1 for entity defined by e0/1 priority 2 for entity defined by e0/1 priority 3 for entity defined by e0/1 priority 4 for entity defined by e0/1 e ntity definition: priority 5 is the last priority for sdram refresh if validated. sdram refresh obtains priority 0 (the first priority) automatically when the first half cycle is spend without access to memory. after reset (e400)h, the rx dma controller has the priority 1 the microprocessor has the priority 2 the tx dma controller has the priority 3 the interrupt controller has the priority 4 e 1 e 0 entity 0 0 rx dma controller 0 1 microprocessor 1 0 tx dma controller 1 1 interrupt controller
STLC5466 56/130 vi.27 - initiate block address register 1 ibar1 (34) h the initiate block address (iba1) is: the 23 more significant bits define one of 8 megawords. (one word comprises two bytes.) the least significant bit defines one of two bytes when the microprocessor selects one byte. example: mhdlc device address inside m p mapping = 100000h initiate block for hdlc1 address inside m p mapping = 110000h ibar1 value = (110000 - 100000)/256 = 100h vi.28 - interrupt queue size register iqsr (36) h bit15 bit8 bit7 bit0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 after reset (0000) h a8/23 : address bits. these 16 bits are the segment address bits of the initiate block (a8 to a23 for the external memory).the offset is zero (a0 to a7 =0). this register concerns the first 32 hdlc controller 1 named hdlc 1 connected to din7/dout7 of the switching matrix. the interrupt queue is common for the first hdlc controller1 and for the second hdlc controller 2. so this register concerns the location of the interrupt queue. the location of the interrupt queue is found from the contents of this first ibar register 1 (34) h . a8/23 : address bits. these 16 bits are the segment address bits of the initiate block (a8 to a23 for the external memory in the mhdlc address space).the offset is zero (a0 to a7 =0). 23 87 0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 0 0 0 0 0 0 0 0 bit15 bit8 bit7 bit0 tbfs0000000hs2hs1hs0ms2ms1ms0cs1cs0 after reset (0000) h cs0/1 : command/indicate interrupt queue size these two bits define the size of command/indicate interrupt queue in external memory. the location is iba + 256 + hdlc queue size + monitor channel queue size (see the initiate block address (iba)). ms0/2 : monitor channel interrupt queue size these three bits define the size of monitor channel interrupt queue in external memory. the location is iba + 256 + hdlc queue size.
57/130 STLC5466 vi.29 - interrupt register ir (38) h this register is read only. when this register is read by the microprocessor, this register is reset (0000) h . if not masked, each bit at 1 generates 1 on int0 pin. bit 0 and bit 5 to 10 are common to 64 hdlc controllers. hs0/2 : hdlc interrupt queue size these three bits define the size of hdlc status interrupt queue in external memory for each channel. the location is iba+256 (see the initiate block address (iba)) tbfs : time base running with frame synchronisation signal tbfs=1, the time base defined by the timer register (see page 84) is running on the rising edge of frame synchronisation signal. tbfs=0, the time base defined by the timer register is running on the rising edge of mclk signal. bit15 bit8 bit7 bit0 nu nu sfco prsr tim int fov int fwar tx fov tx fwar rx fov rx fwar icov mtx mrx c/irx hdlc after reset (0000) h hdlc : hdlc interrupt hdlc = 1, tx hdlc or rx hdlc has generated an interrupt the status is in the hdlc queue. c/irx : command/indicate rx interrupt c/irx = 1, rx command/indicate has generated an interrupt. the status is in the hdlc queue. mrx : rx monitor channel interrupt mrx = 1, one rx monitor channel has generated an interrupt. the status is in the rx monitor channel queue mtx : tx monitor channel interrupt mtx = 1, one or several tx monitor channels have generated an interrupt. transmit monitor interrupt register (tmir) indicates the tx monitor channels which have generated this interrupt. icov : interrupt circular overload icov = 1, one of three circular interrupt memories is completed. hs2 hs1 hs0 hdlc queue size ms2 ms1 ms0 mon queue size cs1 cs0 c/i queue size 000128 words000 128 words 0 0 64 words 0 0 1 256 word 0 0 1 256 word 0 1 128 words 010384 words010 384 words 1 0 192 words 011512 words011 512 words 1 1 256 words 100640 words100 640 words 101768 words101 768 words 110896 words110 896 words 1 1 1 1024 words 1 1 1 1024 words
STLC5466 58/130 vi.30 - interrupt mask register imr (3a) h rxfwar : rx dma controller fifo warning rxfwar = 1, rx dma controller has generated an interrupt, its fifo is 3/4 completed. rxfov : rx dma controller fifo overload rxfov = 1, rx dma controller has generated an interrupt, it cannot transfer data from rx hdlc to external memory, its fifo is completed. txfwar : tx dma controller fifo warning txfwar = 1, tx dma controller has generated an interrupt, its fifo is 3/4 completed. txfov : tx dma controller fifo overload txfov = 1, tx dma controller has generated an interrupt, it cannot transfer data from tx hdlc to external memory, its fifo is completed. intfwar: interrupt controller fifo warning intfwar = 1, interrupt controller has generated an interrupt, its fifo is 3/4 com- pleted. intfov : interrupt controller fifo overload intfov = 1, interrupt controller has generated an interrupt, it cannot transfer sta- tus from dma and gci controllers to external memory, its internal fifo is completed. tim : timer tim = 1, the programmable timer has generated an interrupt. prsr : pseudo random sequence recovered prsr = 1,the pseudo random sequence transmitted by the generator has been recovered by the analyser. sfco : sequence fault counter overload sfco = 1, the fault counter has reached the value ffff(h). bit15 bit8 bit7 bit0 nu nu im13 im12 im11 im10 im9 im8 im7 im6 im5 im4 im3 im2 im1 im0 after reset (ffff) h im13/0 : interrupt mask 0/7 when im0 = 1, hdlc bit is masked. when im1 =1, c/irx bit is masked. when im2 = 1, mrx bit is masked. when im3 = 1, mtx bit is masked. when im4 = 1, icov bit is masked when im5 = 1, rxfwar bit is masked. when im6 = 1, rxfov bit is masked. when im7 = 1, txfwar bit is masked. when im8 = 1, txfov bit is masked. when im9 = 1, intfwar bit is masked. when im10 = 1, intfov bit is masked. when im11 = 1, tim bit is masked. when im12 = 1, prsr bit is masked. when im13 = 1, sfco bit is masked.
59/130 STLC5466 vi.31 - timer register 1 timr1 (3c) h this programmable register indicates the time at the end of which the watch dog delivers logic 1 on the pin wdo (which is an output) but only if the microprocessor does not reset the counter assigned (with the help of wdr bit of idcr (identification and dynamic command register) during the time defined by the timer register.when the microprocessor does not reset the counter, the pin wdo delivers logic 1 as soon as delta t plus programmed time are reached. (delta t from one to two clock periods of the associ- ated counter). remark: the time indicated in this register is obtained when the clock period of the associated counter is 250 mi- croseconds. the minimum programmable time is four clock periods (1 millisecond in this case); the dura- tion of the pulse delivered by the pin wdo is one clock period (250 microseconds). the timer register and its counter can be used as a time base by the microprocessor. an interrupt (tim) is generated at each period defined by the timer register if the microprocessor does not reset the counter. to reset the counter, wdr (bit of idcr) must be set to 1 by the microprocessor. the watch dog or the timer is incremented by the frame synchronisation clock divided by two (tbfs=1) or by a submultiple of mclk signal (tbfs=0; tbfs, bit of interrupt queue size register). example: tbfs=1 if the frame synchronisation clock is at 8 khz, the period of the counter clock is 250 microsec- onds tbfs=0 if mclk clock is at 32768 khz the clock period of the counter is 250 microseconds (inverse of 32768khz divided by 8192). when tsv=1{bit of general configuration register)} this programmable register (timr1) is not signifi- cant. vi.32 - test register tr (3e) h bit15 bit8 bit7 bit0 s3 s2 s1 s0 ms9 ms8 ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 mm1 mm0 0 to 5s 0 to 999ms 0 to 3x0.25ms after reset (0800) h bit15 bit8 bit7 bit0 reservedreserved t15/0 : test bits 0/15 these bits are reserved for the test of the circuit in production.the use of these bits is forbidden.
STLC5466 60/130 vi.33 - general configuration register 2 gcr2 (42) h bit15 bit8 bit7 bit0 nu nu nu nu nu nu nu nu nu swap d6 byp ninit 0 mc1 mc0 after reset (0000) h id 512ms mc0/1 : master clock0/1 mc0/1: these two bits take into account the signal applied on mclk pin. so whatever the fre- quency may be, the internal circuit operates with the appropriate internal clock and the exchang- es between multi-hdlc and sdram are at the master clock frequency. the duration of the pulse named token ring is equal to the period of master clock applied to mclk pin. ninit : not init ninit=1; when the microprocessor writes the sdram register with ninit=1, the sdram will not be initialized. ninit=0; when the microprocessor writes the sdramr register with ninit=0, the sdram will be initialized in accordance with lt0/2 bits (of sdramr). in case of several multi-hdlcs connected to the same memory, only one of them initializes and refreshes the sdram. so the gcr2 registers of these multi-hdlcs are same contents except this bit which initializes the sdram. byp : bypass bypass=1; the write fifo and the read fetch memory located in the microprocessor interface are bypassed. bypass=0; the write fifo and the read fetch memory located in the microprocessor interface are used when the microprocessor accesses the shared memory. d6 : hdlc2 connected to matrix d6=1, the transmit hdlc2 is connected to matrix input 6, the din6 signal is ignored. mc1 mc0 signal applied on mclk pin exchanges between multi-hdlc and sdram with common clock at 0 0 66mhz 66mhz 0 1 50mhz 50mhz 1 0 33mhz 33mhz 1 1 not used not used
61/130 STLC5466 vi.34 - split fetch memory register sfmr (4e) h this register must be programmed after reset before the first sdram access. writing register is forbidden between two sdram accesses. swap swap=1 the first byte (named 2b) of frames received (or transmitted) by the hdlcs is stored in bit 8/15 of the shared memory (or located in bit 8/15); the first bit received is stored in bit 8 of the shared memory. the first bit to be transmitted is located in bit 8 of the shared memory. the second byte (named 2b+1) of the frame received (or transmitted) by the hdlcs is stored in bit 0/7 of the shared memory; the first bit of the second byte received is stored in bit 0 of the shared memory. the ninth bit to be transmitted is located in bit 0 of the shared memory. the bytes named (2b) are located in bit 8/15 of the shared memory; b from 0 to 2047. the bytes named (2b+1) are located in bit 0/7of the shared memory. swap=0 the first byte (named 2b) of frames received (or transmitted) by the hdlcs is stored in bit 0/7 of the shared memory (or located in bit 0/7); the first bit received is stored in bit 0 of the shared memory. the first bit to be transmitted is located in bit 0 of the shared memory. the second byte (named 2b+1) of the frame received (or transmitted) by the hdlcs is stored in bit 8/15 of the shared memory; the first bit of the second received is stored in bit 8 of the shared memory. the ninth bit to be transmitted is located in bit 8 of the shared memory. the bytes named (2b) are located in bit 0/7 of the shared memory; b from 0 to 2047 the bytes named (2b+1) are located in bit 8/15 of the shared memory. bit15 bit8 bit7 bit0 a23 a22 a21 a20 a19 a18 a17 a16 nu nu nu nu nu nu nab ffa after reset (0000) h ffa : fast fetch memory access. this bit is taken into account only when synchronous 386ex micro- processor is selected. ffa = 1; in case of read from synchronous 386ex microprocessor ? if lba delivered by the microprocessor is at1, ? if the word is already in the fetch memory, ? if the write fifo is empty, ? if no current burst due to a previous read access then there is no twait. ffa = 0; in case of read from synchronous 386ex microprocessor with the same conditions de- scribed above there is one twait. nab : no anticipation burst nab = 1. a read burst is generated only when a word required by the microprocessor is not present in the fetch memory. no anticipation is done for potential further accesses. nab = 0. an anticipation is added to the fetch memory management. if one of four words of a burst is read by the microprocessor in the fetch memory and if the following four words are not present and valid in the fetch memory, then the following four words are transferred automatically by anticipation from sdram to the fetch memory.
STLC5466 62/130 vi.35 - time slot assigner address register 2 taar2 (54) h this register concerns the second 32 hdlc controller named hdlc2 connected to input6/output6 of the switching matrix. ? n.b. after software reset (bit 2 of idcr register) or pin reset the automate above mentioned is working. the automate is stopped when the microprocessor writes taar register with hdi = 0. vi.36 - time slot assigner data register 2 tadr2 (56) h this register concerns the second 32 hdlc controller named hdlc2 connected to input6/output6 of the switching matrix a16/23: these 8 bits define two areas of the shared memory; each area is multiple of 64kbytes. the shared memory is split in two parts: the upper part of the shared memory is affected to the first half part of the fetch memory located in the microprocessor interface, the lower part is affected to the second half part of the fetch memory. particular case: a16/23=0. one area of the shared memory is defined, the two parts of the fetch memory are merged. bit15 bit8 bit7 bit0 ts4 ts3 ts2 ts1 ts0 read nu hdi r e s e r v e d after reset (0100) h read : read memory read = 1, read time slot assigner memory 2. read = 0, write time slot assigner memory 2. ts0/4 : time slots0/4 these five bits define one of 32 time slots in which a channel is set-up or not. hdi : hdlc2 init hdi = 1, tsa2 memory, tx hdlc2, tx dma2, rx hdlc2, rx dma2 are reset. an automate writes data from time slot assigner data register 2 (tadr2) (except ch0/4 bits) into each tsa memory location. if the microprocessor reads time slot assigner memory 2 after hdlc2 init, ch0/4 bits of time slot assigner data register are identical to ts0/4 bits of time slot assigner address register 2. hdi = 0, normal state. bit15 bit8 bit7 bit0 v11 v10 v9 v8 v7 v6 v5 v4 v3 v2 v1 ch4 ch3 ch2 ch1 ch0 after reset (0000) h ch0/4 : channel0/4 these five bits define one of 32 channels associated to time slot defined by the previous reg- ister 2 (taar 2 ). v1/8 : validation the logical channel chx is constituted by each subchannel 1 to 8 and validated by v1/8 bit at 1 respectively. v1 to v8 are at 0: the subchannels are ignored. v1 corresponds to the first bit received during the current time slot. v1 at 1: the first bit of the current time slot is taken into account in reception and in transmission the first bit transmitted is taken into account. v8 at 1: the last bit of the current time slot is taken into account in reception the last bit received and in transmission the last bit transmitted in transmission.
63/130 STLC5466 vi.37 - hdlc transmit command register 2 htcr2 (58) h v9 : validation subchannel v 9 = 1, each v1/8 bit is taken into account once every 250 m s. in transmit direction , data is transmitted consecutively during the time slot of the current frame and during the same time slot of the next frame.id est.: the same data is transmitted in two con- secutive frames. in receive direction , hdlc controller fetches data during the time slot of the current frame and ignores data during the same time slot of the next frame. v 9 = 0, each v1/8 bit is taken into account once every 125 m s. v10 : direct mhdlc access if v10 = 1, the rx hdlc controller 2 receives data issued from din9 input during the current time slot (bits validated by v1/8) and dout7 output transmits data issued from the tx hdlc controller 2. if v10 = 0, the rx hdlc controller2 receives data issued from the matrix output 6 during the current time slot; dout7 output delivers data issued from the matrix output 7 during the same current time slot. n.b: if d6 = 1, bit of general configuration register gcr2, the tx hdlc controller 2 is con- nected to matrix input 6 continuously so the hdlc frames can be sent to any dout (i.e. dout0 to dout7) from the tx hdlc controller2. v11 : validation of cb2 pin this bit is not taken into account if csma = 1 (hdlc transmit command register 2). if csma = 0: v11 = 1, contention bus 2 pin is validated and echo 2 pin (which is an input) is not taken into account. v11 = 0, contention bus 2 pin is high impedance during the current time slot (this pin is an open drain output). bit15 bit8 bit7 bit0 ch4 ch3 ch2 ch1 ch0 read nu cf pen csma ncrc f p1 p0 c1 c0 after reset (0000) h read : read command memory read = 1, read command memory. read = 0, write command memory. ch0/4 : these five bits define one of 32 channels of the second 32 hdlc controller named hdlc 2 connected to input6/output6 of the switching matrix. c1/c0 : command bits c1 c0 command bits 0 0 abort; if this command occurs during the current frame, hdlc controller transmits seven 1 immediately, afterwards hdlc controller transmits 1 or flag in accordance with f bit, generates an interrupt and waits new command such as start or continue. if this command occurs after transmitting a frame, hdlc controller generates an interrupt and waits a new command such as start or continue. 0 1 start; tx dma controller is now going to transfer first frame from buffer related to initial de- scriptor. the initial descriptor address is provided by the initiate block located in external memory. 1 0 continue; tx dma controller is now going to transfer next frame from buffer related to next descriptor. the next descriptor address is provided by the previous descriptor from which the related frame had been already transmitted. 1 1 halt; after transmitting frame, hdlc controller transmits 1 or flag in accordance with f bit, generates an interrupt and is waiting new command such as start or continue.
STLC5466 64/130 vi.38 - hdlc receive command register 2 hrcr2 (5a) h c1/c0 : status bits p0/1 : protocol bits f:flag f = 1; flags are transmitted between closing flag of current frame and opening flag of next frame. f = 0; 1 are transmitted between closing flag of current frame and opening flag of next frame. ncrc : crc not transmitted ncrc = 1, the crc is not transmitted at the end of the frame. ncrc =0, the crc is transmitted at the end of the frame. csma : carrier sense multiple access with contention resolution csma = 1, cb2 output and the echo bit ec2 are taken into account during this channel trans- mission by the txhdlc2. csma = 0, cb2 output and the echo bit ec2 are defined by v11 (see time slot assigner data register 2 tadr2(56) h ). pen : csma penalty significant if csma = 1 pen = 1, the penalty value is 1; a transmitter which has transmitted a frame correctly will count (pri +1) logic one received from echo pin before transmitting next frame. (pri, priority class 8 or 10 given by the buffer descriptor related to the frame. pen = 0, the penalty value is 2; a transmitter which has transmitted a frame correctly will count (pri +2) logic one received from echo pin before transmitting next frame. (pri, priority class 8 or 10 given by the transmit descriptor related to the frame). cf : common flag cf = 1, the closing flag of previous frame and opening flag of next frame are identical if the next frame is ready to be transmitted. cf = 0, the closing flag of previous frame and opening flag of next frame are distinct. bit15 bit8 bit7 bit0 ch4 ch3 ch2 ch1 ch0 read ar21 ar20 ar11 ar10 crc fm p1 p0 c1 c0 after reset (0000) h c1 c0 status bits read by the microprocessor 0 0 abort; the microprocessor has written abort or the transmitted frame has been aborted by the hdlc controller2 and it waits new command such as start or continue. 0 1 start; the microprocessor has written start.the hdlc controller2 has not taken into ac- count the command yet. 1 0 continue; the hdlc controller2 has taken into account the command start. tx dma controller is transferring frames. 1 1 continue; tx dma controller is now going to transfer next frame from buffer related to next descriptor. the next descriptor address is provided by the previous descriptor from which the related frame had been already transmitted. p1 p0 transmission mode 00hdlc 0 1 transparent mode 1 (one byte per timeslot); the fill character defined in fcr register is taken into account. 1 0 transparent mode 2 (one byte per timeslot); the fill character defined in fcr register is not taken into account. 1 1 reserved
65/130 STLC5466 read : read command memory read = 1, read command memory. read = 0, write command memory. ch0/4 : these five bits define one of 32 channels of the second 32 hdlc controller2 named hdlc controller2 connected to iinput6/output6 of the switching matrix c1/c0 : command c1/c0 : status bits p0/1 : protocol bits fm : flag monitoring this bit is a status bit read by the microprocessor. fm=1: hdlc controller 2 is receiving a frame or hdlc controller 2 has just received one flag. fm is put to 0 by the microprocessor. crc : crc stored in external memory crc = 1, the crc is stored at the end of the frame in external memory. crc = 0, the crc is not stored into external memory. c1 c0 command bits 0 0 abort; if this command occurs during receiving a current frame, hdlc controller stops the reception, generates an interrupt and waits new command such as start or continue. if this command occurs after receiving a frame, hdlc controller generates an interrupt and waits a new command such as start or continue. 0 1 start; rx dma controller is now going to transfer first frame into buffer related to the initial descriptor. the initial descriptor address is provided by the initiate block located in external memory. 1 0 continue; rx dma controller is now going to transfer next frame into buffer related to next descriptor. the next descriptor address is provided by the previous descriptor from which the related frame had been already received. 1 1 halt; after receiving a frame, hdlc controller stops the reception, generates an interrupt and waits a new command such as start or continue. c1 c0 status bits read by the microprocessor 0 0 abort; the received current frame has been aborted (seven 1 at least have been received) or the microprocessor has written abort. the hdlc controller2 waits a new command such as start or continue 0 1 start; the microprocessor has written start.the hdlc controller2 has not taken into ac- count the command yet. 1 0 continue; rx dma controller is transferring frames 1 1 halt; hdlc controller2 stops the reception, generates an interrupt and waits a new com- mand such as start or continue. p1 p0 transmission mode 00hdlc 0 1 transparent mode 1 (one byte per timeslot); the fill character defined in fcr register is taken into account. 1 0 transparent mode 2 (one byte per timeslot); the fill character defined in fcr register is not taken into account. 1 1 reserved
STLC5466 66/130 ar10 : address recognition10 ar10 = 1, first byte after opening flag of received frame is compared to af0/7 bits of afrdr. if the first byte received and af0/7 bits are not identical the frame is ignored. ar10 = 0, first byte after opening flag of received frame is not compared to af0/7 bits of afrdr register. ar11 : address recognition 11 ar11 = 1, first byte after opening flag of received frame is compared to all 1s.if the first byte received is not all 1s the frame is ignored. ar11 = 0, first byte after opening flag of received frame is not compared to all 1s. ar20 : address recognition 20 ar20 = 1, second byte after opening flag of received frame is compared to af8/15 bits of afrdr regis- ter. if the second byte received and af8/15 bits are not identical the frame is ignored. ar20 = 0, second byte after opening flag of received frame is not compared to af8/15 bits of afrdr reg- ister. ar21 : address recognition 21 ar21 = 1, second byte after opening flag of received frame is compared to all 1s. if the second byte received is not all 1s the frame is ignored. ar21 = 0, second byte after opening flag of received frame is not compared to all 1s. second byte first byte conditions to receive a frame ar21 ar20 ar11 ar10 0 0 0 0 each frame is received without condition. 0 0 0 1 only value of the first received byte must be equal to that of af0/7 bits. 0 0 1 0 only value of the first received byte must be equal to all 1s. 0 0 1 1 the value of the first received byte must be equal either to that of af0/7 or to all 1s. 0 1 0 0 only value of the second received byte must be equal to that of af8/15 bits. 0 1 0 1 the value of the first received byte must be equal to that of af0/7 bits and the value of the second received byte must be equal to that of af8/15 bits. 0 1 1 0 the value of first received byte is must be equal to all 1s and the value of second received byte must be equal to that of af8/15 bits. 0 1 1 1 the value of the first received byte must be equal either to that of af0/7 or to all 1s and the value of the second received byte must be equal to that of af8/15 bits. 1 0 0 0 only the value of the second received byte must be equal to all 1s. 1 0 0 1 the value of the first received byte must be equal to that of af0/7 bits and the value of the second received byte must be equal to all 1s.
67/130 STLC5466 vi.39 - address field recognition address register 2 afrar2 (5c) h the write operation is launched when afrar2 is written by the microprocessor. vi.40 - address field recognition data register 2 afrdr2 (5e) h 1 0 1 0 the value of the first received byte must be equal to all 1s and the value of the second received byte must be equal to 1 also. 1 0 1 1 the value of the first received byte must be equal either to that of af0/7 or to 1 and the value of the second received byte must be equal to all 1s. 1 1 0 0 the value of the second received byte must be equal either to that of af8/15 or to all 1s. 1 1 0 1 the value of the first received byte must be equal to that of af0/7 bits and the value of the second received byte must be equal either to that of af8/15 or to all 1s. 1 1 1 0 the value of the first received byte must be equal to 1 and the value of the second received byte must be equal either to that of af8/15 or to all 1s. 1 1 1 1 the value of the first received byte must be equal either to that of af0/7 or to 1 and the value of the second received byte must be equal either to that of af8/15 or to all 1s. bit15 bit8 bit7 bit0 ch4 ch3 ch2 ch1 cho read amm nu r e s e r v e d after reset (0000) h amm : access to mask memory amm=1, access to address field recognition mask memory. amm=0, access to address field recognition memory. read : read address field recognition memory read=1, read afr memory. read=0, write afr memory. ch0/4 : in reception these five bits define one of 32 channels of the second 32 hdlc controller 2 named hdlc 2 connected to din6/dout6 of the switching matrix. bit15 bit8 bit7 bit0 af15/ afm15 af14/ afm14 af13/ afm13 af12/ afm12 af11/ afm11 af10/ afm10 af9/ afm9 af8/ afm8 af7/ afm7 af6/ afm6 af5/ afm5 af4/ afm4 af3/ afm3 af2/ afm2 af1/ afm1 af0/ afm0 after reset (0000) h af0/15 : address field bits if amm=0 (amm bit of afrar 2 af0/7; first byte received; af8/15: second byte received. these two bytes are stored into address field recognition memory when afrar2 is written by the mi- croprocessor(amm=0). afm0/ 15 : address field bit mask0/15 if amm=1 (amm bit of afrar 2) amf0/7. when ar10=1 (see hrcr2) each bit of the first received byte is compared respectively to afx bit if afmx=0. in case of mismatching, the received frame is ignored. if afmx=1, no comparison between afx and the corresponding received bit. amf8/15. when ar20=1 (see hrcr2) each bit of the second received byte is compared respectively to afy bit if afmy=0. in case of mismatching, the received frame is ignored. if afmy=1, no comparison be- tween afy and the corresponding received bit. these two bytes are stored into address field recognition mask memory when afrar 2 is written by the microprocessor (amm=1). second byte first byte conditions to receive a frame ar21 ar20 ar11 ar10
STLC5466 68/130 vi.41 - fill character register 2 fcr2 (60) h vi.42 - sdram mode register sdramr (72) h when the microprocessor writes in this sdram mode register, the sdram controller initializes the sdram if the ninit bit of gcr2 is at 0 . when the microprocessor reads this register, the sdram controller is not affected. some parameters are frozen: the option field is: burst read and single write. the burst length is 4. the burst data is addressed in sequential mode the programmable parameters are: the 12-bit word sent by the multi-hdlc to initialize the sdram is: for information: bit15 bit8 bit7 bit0 r e s e r v e d fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 after reset (0000) h fc0/7 : fill character (eight bits) in transparent mode m1, two messages are separated by fill characters and the de- tection of one fill character marks the end of a message. bit15 bit8 bit7 bit5 bit4 bit0 t s r nununununununult1lt0nunununu after reset (0030) h lt0/1 : latency mode three configurations are possible: ncas latency can be 1, 2 or 3) bit15 bit11 bit8 bit7 bit5 bit4 bit0 nu nu nu nu 0 0 1 0 0 lt2 lt1 lt0 wt bl2 bl1 bl0 nu nu nu nu 0 0 1 0 0 0 lt1 lt0 0 0 1 0 option field: burst read and single write latency mode wrap type burst length x x 1 0 0 lt2 lt1 lt0 wt bl2 bl1 bl0 tt lt1 lt0 ncas latency 0 0 not allowed 01 1 10 2 11 3
69/130 STLC5466 for information: vi.43 - initiate block address register 2 ibar2 (74) h this register concerns the second 32 hdlc controller 2 named hdlc 2 connected to input6/output6 of the switching matrix. the interrupt queue is common for the first hdlc controller and for the second hdlc controller 2. so this register doesnt concern the location of the interrupt queue.the location of the interrupt queue is found from the contents of the first ibar1 register (34)h. the initiate block address (iba2) is: the 23 more significant bits define one of 8 megawords. (one word comprises two bytes.) the least significant bit defines one of two bytes when the microprocessor selects one byte. example: mhdlc device address inside m p mapping = 100000h initiate block for hdlc2 address inside m p mapping = 310000h ibar2 value = (310000 - 100000)/256 = 2100h lt2 lt1 lt0 ncas latency bl2 bl1 bl0 burst length wt=0 burst length wt=1 0 0 0 r 000 1 1 0 0 1 1 001 2 2 0 1 0 2 010 4 4 0 1 1 3 011 8 8 1 0 0 r 100 r r 1 0 1 r 101 r r 1 1 0 r 110 r r 1 1 1 r 1 1 1 full page r t,s,r : these three bits define the sdram circuit organisation (1word=2bytes)) bit15 bit8 bit7 bit0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 after reset (0000) h a8/23 : address bits. these 16 bits are the segment address bits of the initiate block (a8 to a23 for the external memory in the mhdlc address space).the offset is zero (a0 to a7 =0). 23 87 0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 0 0 0 0 0 0 0 0 tt tsr sdram circuit organization (and shared ram organization) if refresh 0 0 0 (1mx16) sdram circuit; shared ram up to 4m words 2048 cycles / 32ms 0 0 1 (2mx8) sdram circuit; shared ram up to 8m words 4096 cycles / 64ms 0 1 0 (8mx8) sdram circuit; shared ram up to 8m words 4096 cycles / 64ms 0 1 1 (4mx16) sdram circuit; shared ram up to 8m words 4096 cycles / 64ms 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved
STLC5466 70/130 vi.44 - timer register 2 timr2 (7c) h this programmable timer register 2 indicates the period of the super frame synchronisation signal de- livered by sfs pin (which is an output). the duration of the signal is 250 microseconds. the minimum programmable period is 500 microseconds. the clock frequency of the associated counter is the frequency divided by two of fs frame synchronisa- tion signal applied to fs pin (which is an input). bit15 bit8 bit7 bit0 s3 s2 s1 s0 ms9 ms8 ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 mm1 mm0 0 to 15s 0 to 999ms 0 to 3x0.25ms after reset (0780)h id 480 ms
71/130 STLC5466 vii - external registers these registers are located in shared memory. initiate block address registers (ibar1 and ibar2) give respectively the initiate block address (iba1 and iba2) in shared memory. from iba1 the different addresses are obtained: ? initialization block address concerning the first hdlc controller (hdlc1) ? hdlc interrupt queue for the first hdlc controller (hdlc1) and the second (hdlc2) ? mon interrupt queue ? c/i interrupt queue from iba1 only the following address is obtained: ? initialization block address concerning the second hdlc controller (hdlc2) not used bits (nu) are accessible by the microprocessor but the use of these bits by software is not rec- ommended. vii.1 - initialization block in external memory (iba1 and iba2) when direct memory access controller receives start from one of 64 channels, it reads initialization block immediately to know the first address of the first descriptor for this channel. bit 0 of transmit descriptor address (tda low) and bit 0 of receive descriptor address (rda low), are at zero mandatory. this least significant bit is not used by dma controller, the shared memory is al- ways a 16 bit memory for the dma controller. the receive descriptor address (rda) is never modified by the rx dma controller in this initialization block n.b. if several descriptors are used to transmit the current frame then before transmitting frame, tx dma controller stores the address of the first transmit descriptor address (tda) into this initialization block if bof bit is at 1 (see transmit descriptor). descriptor address channel address bit15 bit8 bit7 bit0 ch 0 t iba+00 not used tda high iba+02 transmit descriptor address (tda low) r iba+04 not used rda high iba+06 receive descriptor address (rda low) ch1 t iba+08 not used tda high iba+10 transmit descriptor address (tda low) r iba+12 not used rda high iba+14 receive descriptor address (rda low) ch 2 to ch30 iba+16 to iba+246 ch 31 t iba+248 not used tda high iba+250 transmit descriptor address (tda low) r iba+252 not used rda high iba+254 receive descriptor address (rda low)
STLC5466 72/130 vii.2 - receive descriptor this receive descriptor is located in shared memory. the quantity of descriptors is limited by the memory size only. the 5 first words located in shared memory to rda+00 from rda+08 are written by the microprocessor and read by the dmac only. the 6th word located in shared memory in rda+10 is written by the dmac only during the frame reception and read by the microprocessor. vii.2.1 - bits written by the microprocessor only vii.2.2 - bits written by the rx dmac only 15 14 13 1211109876543210 rda+00 sim ibc eoq size of the buffer (sob) 0 rda+02 not used rba high (8 bits) rda+04 receive buffer address low (16 bits) rda+06 not used nrda high (8 bits) rda+08 next receive descriptor address low (16 bits) rda+10 fr abt ovf fcr c number of bytes received (nbr) sob : size of the buffer associated to descriptor. these 12bits allows to reach 4096 bytes). if sob = 0, dmac goes to next descriptor. rba : receive buffer address. lsb of rba low is at zero mandatory. rda : receive descriptor address. nrda : next receive descriptor address. lsb of nrda low is at zero mandatory. nbr : number of bytes received (up to 4096). ibc : interrupt if the buffer has been completed. ibc=1, the dmac generates an interrupt if the buffer has been completed. eoq : end of queue. eoq=1, the dmac stops immediately its reception generates an interrupt (hdlc = 1 in ir) and waits a command from the hrcr (hdlc receive command register). eoq=0, the dmac continues. sim : signal interrupt mask sim=1, when an event occurs the rx dmac thanks to interrupt controller stores the features of this event in the hdlc interrupt queue but the interrupt register is not written. so there is no interrupt signal on int0 pin. sim=0, when an event occurs the rx dmac thanks to interrupt controller stores the features of this event in the interrupt queue and the hdlc bit of the interrupt register is put at 1. so int0 pin goes to vcc if hdlc bit is not masked. fr abt ovf fcrc definition 1 0 0 0 the frame has been received without error. the end of frame is in this buffer. 1 0 0 1 the frame has been received with false crc. 0 0 0 0 if nbr is different to 0, the buffer related to this descriptor is completed.the end of frame is not in this buffer. 0 0 0 0 if nbr is equal to 0, the rx dmac is receiving a frame.
73/130 STLC5466 vii.2.3 - receive buffer each receive buffer is defined by its receive descriptor. the maximum size of the buffer is 2048 words (1 word=2 bytes) vii.3 - transmit descriptor this transmit descriptor is located in shared memory. the quantity of descriptors is limited by the memory size only. the 5 first words located in shared memory to tda+00 from tda+08 are written by the microprocessor and read by the dmac only. the 6th word located in shared memory in tda+10 is written by the dmac only during the frame reception and read by the microprocessor. vii.3.1 - bits written by the microprocessor only 0 1 0 0 abort. the received frame has been aborted by the remote transmitter or the local microprocessor. 0 1 1 0 overflow of fifo. the received frame has been aborted. 0 1 0 1 the received frame had not an integer of bytes. 15 0 rba first buffer location rba + sob-2 last location available = receive buffer address (rba) + size of the buffer (sob-2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tda+00 bint bof eof eoq number of bytes to be transmitted (nbt) tda+02 not used crcc pri tba high (8 bits) tda+04 transmit buffer address low (16 bits) tda+06 not used ntba high (8 bits) tda+08 next transmit descriptor address low (16 bits) tda+10 cft abt und nbt : number of bytes to be transmitted (up to 4096). tba : transmit buffer address. lsb of tba low is at zero mandatory. tda : transmit descriptor address. ntda : next transmit descriptor address. lsb of ntda low is at zero mandatory. bint : interrupt at the end of the frame or when the buffer is become empty. bint = 1, if eof = 1 the dmac generates an interrupt when the frame has been transmitted; if eof = 0 the dmac generates an interrupt when the buffer is become empty. bint = 0, the dmac does not generate an interrupt during the transmission of the frame. fr abt ovf fcrc definition
STLC5466 74/130 vii.3.2 - bits written by the tx dmac only vii.3.3 - transmit buffer each transmit buffer is defined by its transmit descriptor. the maximum size of the buffer is 2048 words (1 word=2 bytes) bof : beginning of frame bof=1,the transmit buffer associated to this transmit descriptor contains the beginning of frame. the dma controller will store automatically the current descriptor address in the initialization block. bof=0, the dma controller will not store the current descriptor address in the initialization block. eof : end of frame eof = 1,the transmit buffer associated to this transmit descriptor contains the end of frame. eof = 0,the transmit buffer associated to this transmit descriptor does not contain the end of frame eoq : end of queue eoq = 1, the dmac stops immediately its transmission, generates an interrupt (hdlc = 1 in ir) and waits a command from the htcr (hdlc transmit command register). eoq = 0, the dmac continues. crcc : crc corrupted crcc = 1,at the end of this frame the crc will be corrupted by the tx hdlc controller. pri : priority class 8 or 10 pri = 1, if csma/cr is validated for this channel, the priority class is 8. pri = 0, if csma/cr is validated for this channel the priority class is 10. (see register csma) cft : frame correctly transmitted cft = 1, the frame has been correctly transmitted. cft = 0, the frame has not been correctly transmitted. abt : frame transmitting aborted abt = 1, the frame has been aborted by the microprocessor during the transmission. abt = 0, the microprocessor has not aborted the frame during the transmission. und : underrun und = 1, the transmit fifo has not been fed correctly during the transmission. und = 0, the transmit fifo has been fed correctly during the transmission. 15 0 tba first word to transmit tba + x; nbt is odd: x = nbt - 1 nbt is even: x = nbt - 2 last word to transmit
75/130 STLC5466 vii.4 - receive & transmit hdlc frame interrupt this word is located in the hdlc interrupt queue; iqsr register indicates the size of this hdlc interrupt queue located in the external memory. transmitter receiver bit15 bit8 bit7 bit 0 ns a5 tx a4 a3 a2 a1 a0 0 0 0 cft/cfr be/bf halt eoq rrlf/erf ns : new status. before writing the features of event in the external memory the interrupt controller reads the ns bit: if ns = 0, the interrupt controller puts this bit at 1 when it writes the status word of the frame which has been transmitted or received. if ns = 1, the interrupt controller puts icov bit at 1 to generate an interrupt (ir register). when the microprocessor has read the status word, it puts this bit at 0 to acknowledge the new status. this location becomes free for the interrupt controller. a5 : 32 hdlc controller a5 = 1, second 32 hdlc controller (connected to dout6/ din6 of the switching matrix). a5 = 0, first 32 hdlc controller (connected to dout7/ din7 of the switching matrix). tx : tx = 1, transmitter a4/0 : tx hdlc channel 0 to 31 rrlf : ready to repeat last frame in consequence of event such as abort command hdlc, controller is waiting start or continue eoq : end of queue the transmit dma controller has encountered the current transmit descriptor with eoq at 1. dma controller is waiting continue from microprocessor. halt : the transmit dma controller has received halt from the microprocessor; it is waiting contin- ue from microprocessor. be : buffer empty if bint bit of transmit descriptor is at 1, the transmit dma controller puts be at 1 when the buffer has been emptied. cft : correctly frame transmitted a frame has been transmitted. this status is provided only if bint bit of transmit descriptor is at 1. cft is located in the last descriptor if several descriptors are used to define a frame. tx : tx = 0, receiver a4/0 : rx hdlc channel 0 to 31 erf : error detected on received frame an error such as crc not correct, abort, overflow has been detected. eoq : end of queue the receive dma controller has encountered the current receive descriptor with eoq at 1. dma controller is waiting continue from microprocessor. halt : the receive dma controller has received halt or abort (on the outside of frame) from the microprocessor; it is waiting continue or start from the microprocessor. bf : buffer filled if ibc bit of receiver descriptor is at 1, the receive dma controller puts bf at1 when it has filled the current buffer with data from the received frame.
STLC5466 76/130 vii.5 - receive command / indicate interrupt vii.5.1 - receive command / indicate interrupt when tsv = 0 time stamping not validated (bit of gcr register) this word is located in the command/indicate interrupt queue; iqsr register indicates the size of this interrupt queue located in the external memory. cfr : correctly frame received cfr =1, a receive frame is ended with a correct crc. the end of the frame is located in the last descriptor if several descriptors. bit15 bit8 bit7 bit 0 ns nu s1 s0=0 g0 a2 a1 a0 nu nu c6 c5 c4 c3 c2 c1 ns nu s1 s0=1 g0 a2 a1 a0 nu nu a e s1 s2 s3 s4 ns : new status. before writing the features of event in the external memory the interrupt controller reads the ns bit: if ns = 0, the interrupt controller puts this bit at 1 when it writes the new primitive which has been received. if ns = 1, the interrupt controller puts icov bit at 1 to generate an interrupt (ir register). when the microprocessor has read the status word, it puts this bit at 0 to acknowledge the new status. this location becomes free for the interrupt controller. g0 : g0 = 0, gci 0 corresponding to din4 input and dout4 output. g0 = 1, gci 1 corresponding to din5 input and dout5 output. a2/0 : command/indicate channel 0 to 7 being owned by gci 0 or gci 1 s1/0 : primitive or 6 bit word or ais received c6/1 : new primitive received twice consecutively. case of s0=s1=0 a, e, s1/s4 6 bits received twice consecutively. case of s0=1 s1=0. s1 s0 g0 word stored in shared memory 0 0 0 primitive c1/6 received from gci multiplex 0 corresponding to din4 0 0 1 primitive c1/6 received from gci multiplex 1 corresponding to din5 0 1 0 a, e, s1/s4 bits from any input timeslot switched to one timeslot 4n+3 of gci multiplex 0 with- out outgoing to dout4 0 1 1 a, e, s1/s4 bits from any input timeslot switched to one timeslot 4n+3 of gci 1 without outgo- ing to dout5 1 0 0 ais detected during more 30 ms from any input timeslot and switched to b1, b2 channels (16 bits) of the gci multiplex 0 (dout4) in transparent mode or not 1 0 1 ais detected during more 30 ms from any input timeslot and switched to b1, b2 channels (16 bits) of the gci multiplex 1 (dout5) in transparent mode or not. 1 1 0 reserved
77/130 STLC5466 vii.5.2 - receive command / indicate interrupt when tsv = 1 time stamping validated (bit of gcr register) these two words are located in the command/indicate interrupt queue; iqsr register indicates the size of this interrupt queue located in the external memory. vii.6 - receive monitor interrupt vii.6.1 - receive monitor interrupt when tsv = 0 tsv: time stamping not validated (bit of gcr register) these two words are transferred into the monitor interrupt queue; iqsr register indicates the size of this interrupt queue located in the external memory. bit15 bit8 bit7 bit 0 ns nu nu nu g0 a2 a1 a0 nu nu c6 c5 c4 c3 c2 c1 t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 ns : new status. before writing the features of event in the external memory the interrupt controller reads the ns bit: if ns = 0, the interrupt controller puts this bit at 1 when it writes the new primitive which has been received. if ns = 1, the interrupt controller puts icov bit at 1 to generate an interrupt (ir register). when the microprocessor has read the status word, it puts this bit at 0 to acknowledge the new status. this location becomes free for the interrupt controller. g0 : g0 = 0, gci 0 corresponding to din4 input and dout4 output. g0 = 1, gci 1 corresponding to din5 input and dout5 output. a2/0 : command/indicate channel 0 to 7 being owned by gci 0 or gci 1 c6/1 : new primitive received twice consecutively t15/0 : binary counter value when a new primitive is occurred. bit15 bit8 bit7 bit 0 ns g0 a2 a1 a0 odd a f l m18 m17 m16 m15 m14 m13 m12 m11 m8 m7 m6 m5 m4 m3 m2 m1 ns : new status. before writing the features of event in the external memory the interrupt controller reads the ns bit: if ns = 0, the interrupt controller stores two new bytes m1/8 and m11/18 then puts ns bit at 1 when it writes the status of these two bytes which has been received. if ns = 1, the interrupt controller puts icov bit at 1 to generate an interrupt (ir register). g0 : g0 = 0, gci 0 corresponding to din4 input and dout4 output. g0 = 1, gci 1 corresponding to din5 input and dout5 output. l : last byte l=1, two cases: if odd = 1, the following word of the interrupt queue contains the last byte of message. if odd =0, the last byte of message has been stored at the previous access of the interrupt queue (concerning this channel). l=0, the following word and the previous word does not contain the last byte of message. f:first byte f=1, the following word contains the first byte of message. f=0, the following word does not contain the first byte of message.
STLC5466 78/130 in case of v* protocol odd,a,f,l bits are respectively 1,0,1,1. vii.6.2 - receive monitor interrupt when tsv = 1 tsv: time stamping validated (bit of gcr register) these four words are located in the monitor interrupt queue; iqsr register indicates the size of this in- terrupt queue located in the external memory. a : abort a=1, received message has been aborted. odd : odd byte number odd = 1, one byte has been written in the following word. odd = 0, two bytes have been written in the following word. m1/8 : new byte received twice consecutively if gci protocol has been validated. byte received once if v* protocol has been validated. m11/18 : next new byte received twice consecutively if gci protocol has been validated. this byte is at 1 in case of v* protocol. bit15 bit8 bit7 bit 0 ns g0 a2 a1 a0 odd a f l m18 m17 m16 m15 m14 m13 m12 m11 m8 m7 m6 m5 m4 m3 m2 m1 t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 0000000000000000 ns : new status. before writing the features of event in the external memory the interrupt controller reads the ns bit: if ns = 0, the interrupt controller stores two new bytes m1/8 and m11/18 then puts ns bit at 1 when it writes the status of these two bytes which has been received. if ns = 1, the interrupt controller puts icov bit at 1 to generate an interrupt (ir register). g0 : g0 = 0, gci 0 corresponding to din4 input and dout4 output. g0 = 1, gci 1 corresponding to din5 input and dout5 output. l : last byte l=1, two cases: if odd = 1, the following word of the interrupt queue contains the last byte of message. if odd =0, the last byte of message has been stored at the previous access of the interrupt queue (concerning this channel). l=0, the following word and the previous word does not contain the last byte of message. f:first byte f=1, the following word contains the first byte of message. f=0, the first byte of message is not the following word. a : abort a=1, received message has been aborted. odd odd byte number odd = 1, one byte has been written in the following word. odd = 0, two bytes have been written in the following word. m1/8 : new byte received twice consecutively if gci protocol has been validated. byte received once if v* protocol has been validated. m11/18 : next new byte received twice consecutively if gci protocol has been validated. this byte is at 1 in case of v* protocol. t15/0 : binary counter value when a new primitive is occurred.
79/130 STLC5466 viii - tqfp176 package mechanical data tqfp176 (24x24x1.40mm) dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.003 0.008 d 26.00 1.024 d1 24.00 0.945 d3 21.50 0.846 e 0.50 0.019 e 26.00 1.024 e1 24.00 0.945 e3 21.50 0.846 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.0393 k 3.5 (min.), 7 (max.) a a2 a1 b c 44 45 88 89 132 133 176 e3 d3 e1 e d1 d e 1 pin 1 identification k b tqfp176m l l1 seating plane 0.076mm .003 inch outline and mechanical data
STLC5466 80/130 ix - figures and timing see following document these figures must be located in the following paragraphs: figure 1-1: mhdlc block diagram in paragraph ii figure 1-2: variable delay through the matrix with itdm=1 in paragraph iii 5.1 figure 1-3: variable delay through the matrix with itdm=0 in paragraph iii 5.1 figure 1-4: constant delay through the matrix with si=1 in paragraph iii 5.1 figure 1-5: downstream switching at 32 kb/s in paragraph iii 1.7 figure 1-6: upstream switching at 32 kb/s in paragraph iii 1.7 figure 1-7: upstream and downstream switching at 16 kbit/s in paragraph iii 1.8 figure 1-8: d,c/i and monitor channel path in paragraph iii 3.3 figure 1-9: gci channel to/from isdn channel in paragraph iii 5 figure 1-10: from gci channels to isdn channels in paragraph iii 5 figure 1-11: from isdn channels to gci channels in paragraph iii 5 figure 1-12: multi-hdlc connected to mp with multiplexed buses in paragraph iii 6.2.3 figure 1-13: multi-hdlc connected to mp with non multiplexed buses in paragraph iii 6.2.3 figure 1-14: microprocessor interface for intel 80c188 in paragraph iii 6.2.3 figure 1-15: microprocessor interface for intel 80c186 in paragraph iii 6.2.3 figure 1-16: microprocessor interface for morola 68000 in paragraph iii 6.2.3 figure 1-17: microprocessor interface for morola 68020 in paragraph iii 6.2.3 figure 1-18: microprocessor interface for st9 in paragraph iii 6.2.3 figure 1-19: microprocessor interface for intel 386ex in paragraph iii 6.2.3 figure 1-20: ex1; different clocks for multi-hdlc and mp in paragraph iii 6.2.3 figure 1-21: ex2; synchronous clock for multi-hdlc and mp in paragraph iii 6.2.3 figure 1-22: 4mx16 sdram memory organisation in paragraph iii 7.4.1 figure 1-23: first example, 8mx16 sdram memory organisation in paragraph iii 7.4.2 figure 1-24: second example, 8mx16 sdram memory organisation in paragraph iii 7.4.3 figure 1-25: third example, 8mx16 sdram memory organisation in paragraph iii 7.4.4 figure 1-26: chain of n multi-hdlc components in paragraph iii 8 figure 1-27: mhdlc clock generation in paragraph iii 9.1 figure 1-28: vcxo frequency synchronization in paragraph iii 9.2 figure 1-29: the three circular interrupt memories in paragraph iii 10.5
81/130 STLC5466 list of figures 1 figures associated with text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 1-1: mhdlc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 1-2: variable delay through the matrix with itdm=1 . . . . . . . . . . . . . . . . . . . . 84 figure 1-3: variable delay through the matrix with itdm=0 . . . . . . . . . . . . . . . . . . . . 85 figure 1-4: constant delay through the matrix with si=1. . . . . . . . . . . . . . . . . . . . . . . 86 figure 1-5: downstream switching at 32 kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 1-6: upstream switching at 32 kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 1-7: upstream and downstream switching at 16 kbit/s . . . . . . . . . . . . . . . . . . 89 figure 1-8: d, c/i and monitor channel path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 1-9: gci channel to/from isdn channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 1-10: from gci channels to isdn channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 1-11: from isdn channels to gci channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 1-12: multi-hdlc connected to mp with multiplexed buses. . . . . . . . . . . . . . . . 94 figure 1-13: multi-hdlc connected to mp with non multiplexed buses . . . . . . . . . . . . 94 figure 1-14: microprocessor interface for intel 80c188 . . . . . . . . . . . . . . . . . . . . . . . 95 figure 1-15: microprocessor interface for intel 80c186 . . . . . . . . . . . . . . . . . . . . . . . 95 figure 1-16: microprocessor interface for morola 68000 . . . . . . . . . . . . . . . . . . . . . 96 figure 1-17: microprocessor interface for morola 68020 . . . . . . . . . . . . . . . . . . . . . 96 figure 1-18: microprocessor interface for st9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 1-19: microprocessor interface for intel 386ex. . . . . . . . . . . . . . . . . . . . . . . . 97 figure 1-20: ex1; different clocks for multi-hdlc and mp . . . . . . . . . . . . . . . . . . . . . . 98 figure 1-21: ex2; synchronous clock for multi-hdlc and mp . . . . . . . . . . . . . . . . . . . 98 figure 1-22: 4mx16 sdram memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 1-23: first example, 8mx16 sdram memory organisation . . . . . . . . . . . . . . . 100 figure 1-24: second example, 8mx16 sdram memory organisation . . . . . . . . . . . . 101 figure 1-25: third example, 8mx16 sdram memory organisation . . . . . . . . . . . . . . 102 figure 1-26: chain of n multi-hdlc components . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 1-27: mhdlc clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 1-28: vcxo frequency synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 1-29: the three circular interrupt memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2 clock and tdms timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 06 figure 2-1: clocks received and delivered by the multi-hdlc . . . . . . . . . . . . . . . . . 106 figure 2-2: synchronization signals received by the multi-hdlc . . . . . . . . . . . . . . . 107 figure 2-3: gci synchro signal delivered by the multi-hdlc . . . . . . . . . . . . . . . . . . 108 figure 2-4: v* synchronisation signal delivered by the multi-hdlc . . . . . . . . . . . . . 109 3 sdram memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 0 figure 3-1: signals exchanged between sdram controller and sdram. . . . . . . . . 110 4 microprocessor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 4-1: st 9 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 4-2: st 9 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 4-3: st10 (c16x) read cycle; multiplexed a/d . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 4-4: st10 (c16x) write cycle; multiplexed a/d . . . . . . . . . . . . . . . . . . . . . . . . 114
STLC5466 82/130 figure 4-5: st10 (c16x) read cycle; demultiplexed a/d . . . . . . . . . . . . . . . . . . . . . . 115 figure 4-6: st10 (c16x) write cycle; demultiplexed a/d . . . . . . . . . . . . . . . . . . . . . . 116 figure 4-7: 80c188 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 4-8: 80c188 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 4-9: 80c186 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 4-10: 80c186 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 4-11: 386ex read cycle (lba# at vdd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 4-12: 386ex write cycle (lba# at vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 4-13: 386ex; nrdy versus lba# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 4-14: 68000 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 4-15: 68000 write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 4-16: 68020 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 4-17: 68020 write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5 masterclock and token ring timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 5-1: masterclock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 5-2: token ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
83/130 STLC5466 1 figures associated with text figure 1-1: mhdlc block diagraml dout 4 din 4 din 2 din 1 din 0 dout 3 dout 2 dout 1 dout 0 din 7 din 5 din 6 din 3 dout 6 dout 5 dout 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 d7 gci0 gci1 v10a v10a gci0 gci1 ndis tx gci v10b din 9 din 8 cb1 ec1 cb2 ec2 7 d6 v10a v10b v10b switching matrix n x 64 kb/s scrambler/descrambler for 32 channels pseudo random sequence analyser pseudo random sequence generator first 32 rx hdlc with address recognition 32 rx dmac second 32 rx hdlc with address recognition 32 rx dmac second 32 tx hdlc with csma cr for contention bus 32 tx dmac first 32 tx hdlc with csma cr for contention bus 32 tx dmac bus arbitration first time slot assigner second time slot assigner rx gci internal bus microprocessor interface sdram controller v10a, bit v10 of tadr1 v10b, bit v10 of tadr2 d6, bit of gcr2 d7, bit of gcr1
STLC5466 84/130 figure 1-2: variable delay through the matrix with itdm=1 1)case: if otsy > itsx + 2, then variable delay is: otsy - itsx time slots its0 its31 ots31 its31 its0 input output (otsy -itsx) itsx itsx+1 itsx+2 otsy y > x+ 2 variable delay 2)case: if itsx otsy itsx+2, then variable delay is: otsy-itsx+32 time slots its0 its31 ots31 its31 its0 input output itsx itsx+1 itsx+2 otsy variable delay: otsy otsy - itsx + 32 timeslots 32 timeslots 3)case: if otsy < itsx, then variable delay is: 32 - (itsx - otsy) time slots its0 its31 ots31 its31 its0 input output itsx otsy y < x variable delay: otsy 32 - (itsx - otsy) timeslots 32 timeslots itsx itsx ots0 ots0 ots0 frame n frame n + 1 x y x+2 frame frame frame frame frame frame
85/130 STLC5466 figure 1-3: variable delay through the matrix with itdm=0 1)case: if otsy > itsx + 1, then variable delay is: otsy - itsx time slots its0 its31 ots31 its31 its0 input output (otsy -itsx) itsx itsx+1 itsx+2 otsy y > x+ 1 variable delay 2)case: if itsx otsy itsx+2, then variable delay is: otsy-itsx+32 time slots its0 its31 ots31 its31 its0 input output itsx itsx+1 itsx+2 otsy variable delay: otsy otsy - itsx + 32 timeslots 32 timeslots 3)case: if otsy < itsx, then variable delay is: 32 - (itsx - otsy) time slots its0 its31 ots31 its31 its0 input output itsx otsy y < x variable delay: otsy 32 - (itsx - otsy) timeslots 32 timeslots itsx itsx ots0 ots0 ots0 frame n frame n + 1 x y x+1 frame frame frame frame frame frame
STLC5466 86/130 figure 1-4: constant delay through the matrix with si=1 its0 its31 ots0 ots31 ots31 its0 its31 1 + 32 timeslots + 0 =33 timeslots 32 - 0 + 32 + 31 = 95 timeslots max constant delay = 95timeslots constant delay = (32 - itsx) + 32 + otsy 0 x 31 0 y 31 its: input timeslot ots: output timeslot (32 -itsx) + 32 + otsy = constant its0 its31 frame n frame n+1 frame n+2 min constant delay = 33ts delay
87/130 STLC5466 figure 1-5: downstream switching at 32 kb/s dout 4 din 0 dout 2 din 2 internal commands switching at 32 kb/s dout 5 din 1 dout 3 din 3 din0 din2 dout2 dout4 internal command if sw0=1 dout4 (gci 0) 3.9 m s 4 bit shifting dout 5 dout 4 din0 din2 not used din 1 din3 not used multi hdlc stlc 5466 sw0=1 sw1=1 4 bit shifting (gci 0) (gci 1) dout2 dout3 a b free c free free mon d c/i d de a a a b b b c c c d d d e c/i ae b1 b2 mon d c/i ae
STLC5466 88/130 figure 1-6: upstream switching at 32 kb/s dout 0 din4 dout6 din6 switching at 32 kb/s dout1 din 5 multi hdlc stlc 5466 din4 (gci 0) dout6 din6 = shifted dout6 dout0 a free b free c free d free e dc ba b1 b2 mon d c/i gci1 gci 0 from dout6 d c b axyz b2 gci 1 b1 gci 0 b2 gci 0 b1 gci 1 b2 gci 1 dc b a xy b2 gci1 b1 gci 0 b2 gci 0 b1 gci 1 timeslot (3.9 m s) internal loopback and 4 bit shifting (2+2) by software
89/130 STLC5466 figure 1-7: upstream and downstream switching at 16 kbit/s tdm side tsy of any tdm can be programmable with y comprised between 0 and 31. tsy d11 d12 d21 d22 d31 d32 d41 d42 gci side n: gci channel number, 0 to 1 d11 ts 16n+3 d12 c1 c2 c3 c4 a e d21 ts 16n+7 d22 c1 c2 c3 c4 a e d31 ts 16n+11 d32 c1 c2 c3 c4 a e d41 ts 16n+15 d42 c1 c2 c3 c4 a e
STLC5466 90/130 figure 1-8: d, c/i and monitor channel path 16 rx c/i 16 rx mon 16 tx c/i 16 tx mon gci channel definition switching 0 1 2 3 4 5 6 7 16d channels from tx hdlc1 16d channels to rx hdlc1 interrupt controller din 4 din 5 gci0 gci1 dout 4 dout 5 gci0 gci1 internal bus matrix from tx hdlc2 0 1 2 3 4 5 6 7 to rx hdlc 2 from/ to from/to sdram
91/130 STLC5466 figure 1-9: gci channel to/from isdn channel tdm side pcm at 2 mb/s m: isdn channel number, 0 to 9 if tdm at 4 mb/s odd timeslot or even timeslot can be selected ts3m b1 b1 b1 b1 b1 b1 b1 b1 b1 ts3m+1 b2 b2 b2 b2 b2 b2 b2 b2 ts3m+2 d d a e s1 s2 s3 s4 gci side n: gci channel number, 0 to 7 b1 ts4n b1 b1 b1 b1 b1 b1 b1 b1 b2 ts4n+1 b2 b2 b2 b2 b2 b2 b2 m1 ts4n+2 m2 m3 m4 m5 m6 m7 m8 d ts4n+3 d c1 c2 c3 c4 a e scrambler / descrambler scrambler / descrambler six bit word primitive command indicate controllers rx tx monitor controllers tx rx c/i interrupt queue located in shared memory microprocessor mon interrupt queue located in shared memory
STLC5466 92/130 figure 1-10: from gci channels to isdn channels tdm 0, 2 if pcm at 4 mb/s gci side din4/5 scrambler up to 32 switching matrix rx mon controllers up to 16 c/i interrupt queue, mon interrupt queue, located in shared memory microprocessor rx c/i controllers up to 16 for primitives interrupt controller extension tx c/i controllers up to 16 for a, e, s1 to s4 sbv 1 scr d, a, e s1 to s4 b1, b2 by timeslot for the 16 controllers
93/130 STLC5466 figure 1-11: from isdn channels to gci channels tdm 0, 2 if pcm at 4 mb/s gci side dout4/5 descrambler up to 32 switching matrix tx mon controller up to 16 primitives c/i interrupt queue, located in shared memory microprocessor ais detection up to 16 isdn channels interrupt controller tx c/i controller up to 16 primitives scr a, e, s1 to s4 b1, b2 by timeslot extension rx c/i controller up to 16 isdn channels b1, b2 d a, e, mon c/i b1, b2 (16 bits)
STLC5466 94/130 figure 1-12: multi-hdlc connected to m p with multiplexed buses figure 1-13: multi-hdlc connected to m p with non multiplexed buses inter face sdram inter face bus arbitration st9/10 intel motorola 8/16 bits synchronous dynamic ram (organised by 16 bits) multiplex address/data bus address bus data bus multi-hdlc internal bus m p m p inter face ram inter face bus arbitration intel motorola 8/16/32 bits address bus data bus address bus data bus multi-hdlc internal bus st10 synchronous dynamic ram (organised by 16 bits) m p m p
95/130 STLC5466 figure 1-14: microprocessor interface for intel 80c188 figure 1-15: microprocessor interface for intel 80c186 int0/1 ad0/7 a8/19 ale nrd nwr ardy cs0/1 nreset wdo intel 80c188 interface m p int0/1 ad0/15 a16/19 ale nrd nwr ardy cs0/1 nreset wdo intel 80c186 interface m p nbhe
STLC5466 96/130 figure 1-16: microprocessor interface for morola 68000 figure 1-17: microprocessor interface for morola 68020 int0/1 ad0/15 a1/23 nas nlds nuds r/nw cs0/1 nreset wdo motorola 68000 interface m p ndtack int0/1 ad0/15 a0/23 nas nds r/nw size0/1 cs0/1 nreset wdo motorola 68020 interface m p ndsack0/1
97/130 STLC5466 figure 1-18: microprocessor interface for st9 figure 1-19: microprocessor interface for intel 386ex int0/1 ad0/7 a8/15 nas nds r/nw cs0/1 nreset wdo st9 interface m p wait int0/1 d0/15 a1/23 nads wnrd nlba nrdy ncs0/2 nreset wdo nbhe, nble 386extb m p interface STLC5466 clkout
STLC5466 98/130 1.1 microprocessor, mhdlc, sdram clock distribution figure 1-20: ex1; different clocks for multi-hdlc and m p figure 1-21: ex2; synchronous clock for multi-hdlc and m p external clock generation for multi-hdlc and sdram multi-hdlc STLC5466 shared memory sdram m p sdram bus m p bus clk mclk external clock generation for m p mclk: master clock of the multi-hdlc and clk clock of the sdram are the same mandatory. multi-hdlc STLC5466 shared memory sdram internally 50/2 = 25mhz m p 386extb sdram bus m p bus clk mclk external clock generation 50 mhz mclk, master clock of the multi-hdlc, master clock of the m p and clk clock of the sdram are the same.
99/130 STLC5466 1.2 memory obtained with 1m x16 sdram circuit the address bits delivered by the multi-hdlc for 1m x n sdram circuits are: adm11 for bank select corresponding with a20 delivered by the m p adm0/10 for row address inputs corresponding with a9/19 delivered by the m p adm0/7 for column address inputs corresponding with a1/8 delivered by the m p figure 1-22: 4mx16 sdram memory organisation signals a22 a21 signals a0 (or equivalent) nce3 1 1 nce2 1 0 nce1 0 1 udqm 1 nce0 0 0 ldqm 0 0 7 nce2 nce1 nce0 ldqm udqm nce3 1 2 6 4 5 3 dm0/7 dm8/15 adm0/11, nwe, nras, ncas, mclk are connected to each circuit 1m x 16 circuit two banks 512 kwords (16 bits) by bank
STLC5466 100/130 1.3 memory obtained with 2m x 8 sdram circuit the address bits delivered by the multi-hdlc for 2m x n sdram circuits are: adm11 for bank select corresponding with a21 delivered by the m p adm0/10 for row address inputs corresponding with a10/20 delivered by the m p adm0/8 for column address inputs corresponding with a1/9delivered by the m p figure 1-23: first example, 8mx16 sdram memory organisation signals a23 a22 signals a0 nlds nuds nce3 1 1 nce2 1 0 nce1 0 1 udqm 1 0 1 nce0 0 0 ldqm 0 1 0 0 7 nce2 nce1 nce0 ldqm udqm nce3 1 2 6 4 5 3 dm0/7 dm8/15 adm0/11, nwe, nras, ncas, mclk are connected to each circuit 2m x 8 circuit: two banks 1mbyte by bank 2m x16 with 2 circuits
101/130 STLC5466 1.3.0.1 memory obtained with 8m x 8 sdram circuit: the address bits delivered by the multi-hdlc for 8m x n sdram circuits are: adm12/13 for bank select corresponding with a22/23 delivered by the m p adm0/11 for row address inputs corresponding with a10/21 delivered by the m p adm0/8 for column address inputs corresponding with a1/9 delivered by the m p figure 1-24: second example, 8mx16 sdram memory organisation signals a0 nlds nuds udqm 1 0 1 ldqm 0 1 0 8m x 16 with 2 circuits nce ldqm 0 1 dm0/7 dm8/15 udqm adm0/13, nce, nwe, nras, ncas, mclk are connected to each circuit 8m x 8 circuit: four banks 2mbytes by bank
STLC5466 102/130 1.3.0.2 memory obtained with 4m x 16 sdram circuit: the address bits delivered by the multi-hdlc for 4m x n sdram circuits are: adm12/13 for bank select corresponding with a21/22 delivered by the m p adm0/11 for row address inputs corresponding with a9/20 delivered by the m p adm0/7 for column address inputs corresponding with a1/8 delivered by the m p figure 1-25: third example, 8mx16 sdram memory organisation signals a23 signals a0 nlds nuds nce1 1 udqm 1 0 1 nce0 0 ldqm 0 1 0 7 nce0 ldqm udqm nce1 6 4 5 dm0/7 dm8/15 adm0/13, nwe, nras, ncas, mclk are connected to each circuit 4m x16 circuit
103/130 STLC5466 figure 1-26: chain of n multi-hdlc components tri tro tri tro tri tro mhdlc 0 mhdlc 1 mhdlc n ram m p m p bus sdram bus
STLC5466 104/130 figure 1-27: mhdlc clock generation frame a clock a frame b clock b select a or b int1 reset supervision deactivation fscgci fscv* syn1 syn0 frame clock hcl clock selection clock adaptation ref. clock to the internal a or b selected dclk (selb) (bsel) mhdlc (csd) clock general configuration register (gcr) clock lack detection from 250 m s at reset frame a and clock a are selected
105/130 STLC5466 figure 1-28: vcxo frequency synchronization figure 1-29: the three circular interrupt memories f/p ref/8 vcxo low pass filter vcxo-out vcxo-in oux ref=4096 khz mhdlc evm if f=15360 khz, p=30 if f=16384 khz, p=32 f=15360 khz or 16384 khz iba1 iba1+256 iba1+256 +hdlc iba1+256 +hdlc +mon queue size queue size queue size iba1+254 initialization block 1 hdlc interrupt queue for 64 tx- channels and 64 rx channels mon interrupt queue for 16 rx mon chan- nels c/i interrupt queue for 16 rx c/i channels
STLC5466 106/130 2 clock and tdms timing 2.1 synchronization signals delivered by the system for one of three different input synchronizations which is programmed, fscg and fscv* signals deliv- ered by the multi-hdlc are in accordance with the figure hereafter: figure 2-1: clocks received and delivered by the multi-hdlc tx parameter t min. t typ t max unit t1 clock period if 4096 khz (3072) clock period if 8192 khz (6144) 239 (320) 120 (158) 244 (325) 122 (162) 249 (330) 125 (165) ns ns t2 delay between clock a and clock b - 60 0 +60 ns t3 set up time frame a/clock a 10 t1-10 ns t4 hold time frame a (or b)/clock a (or b) 10 t1-10 ns t4gci duration of frame a (or b) 10 125000-(t1-10) ns t5 clock ratio t5h/t5l 75% 100% 125% % t6 duration of fscg 488 (650) ns clock a frame a or b 7 6 1 0 5 4 3 1) sy mode bit3 bit1 bit0 bit7 bit6 bit5 bit4 time slot 31 (if 2048 kbit/s) time slot 0 2) gci mode 3) v* mode din 0/8, echo d0ut 0/7, cb tdmo/7 fscg delivered by the circuit fsc v* delivered by the circuit frame (a or b) frame a (or b) t1 t5h t5l t3 t4 t3 t4 t3 t4 gci t2 clock b if fs=fscg time slot 23 (if 1536 kbit/s) t6 the four multiplex configuration registers are at zero (no delay).
107/130 STLC5466 2.2 tdm synchronization figure 2-2: sychronization signals received by the multi-hdlc parameter t min t typ t max unit t1 dclk clock period if 4096 khz (3072) dclk clock period if 2048 khz (1536) id clocka or b (t min) 244 (325) 488 (651) id clocka or b (t max) ns ns t2 delay between clock a or b and dclk (30pf) 530ns t3 set up time fs/dclk 20 t1-20 ns t4 hold time fs/dclk 20 ns t5 duration fs 244 (325) 125 000 -244 ns t6 dclk to data 50 pf dclk to data 100 pf 50 100 ns ns t7 set up time data/dclk 20 ns t7 hold time data/dclk 20 ns t8 set up echo/dclk (rising edge) 155 ns t9 hold time echo/dclk (rising edge) 205 ns the four multiplex configuration registers are at zero (no delay between fs and multiplexes). dclk delivered by din 0/8 fs received by dout 0/7, cb bit0, time slot 0 the multi-hdlc the multi-hdlc bit7, time slot 31 t1 t3 t4 t5 t6 t7 t7 t2 clock a (or b) echo t8 t9
STLC5466 108/130 2.3 gci interface figure 2-3: sychronization signals delivered by the multi-hdlc parameter t min t typical t max t1 dclk clock period if 4096 khz (3072) dclk clock period if 2048 khz (1536) id clocka or b (t min) 244 (325) 488 (651) id clocka or b (t max) t3 dclk to fscg 20 t5 duration fs 244 125000-244 t6 dclk to data 50 pf dclk to data 100 pf 50 100 t7 set up time data/dclk 20 t7 hold time data/dclk 20 the four multiplex configuration registers are at zero (no delay between fs and multiplexes). dclk delivered din 0/8 fscg delivered dout 0/7, cb bit0, time slot 0 by the multi-hdlc by the multi-hdlc ch 0 ch 1 ch7 din4/5 125 m s mon d c/i ae b1 b2 dout4/5 fs received by the multi-hdlc t3 t3 t6 t7 t7 t1 if fscg connected to fs
109/130 STLC5466 2.4 v* interface figure 2-4: v* synchronisation signal delivered by the multi-hdlc parameter t min t typical t max t1 clock period 4096 khz 244 t3 dclk to fscv* 20 t5 duration fscv* 244 t6 clock to data 50 pf clock to data 100 pf 50 100 t7 set up time data/dclk 20 t7 hold time data/dclk 20 parameter t min t typical t max the four multiplex configuration registers are at zero (no delay between fs and multiplexes) dclk delivered din 0/8 fscv* delivered dout 0/7, cb bit3, time slot 31 by the multi-hdlc by the multi-hdlc ch 0 ch 1 ch7 din4/5 125 m s mon d c/i at b1 b2 dout4/5 fs received by the multi-hdlc t3 t3 t1 if fscg is connected to fs t7 t7
STLC5466 110/130 3 sdram memory timing figure 3-1: signals exchanged between sdram controller and sdram parameter t min t max unit t 1/t= 33, 50 or 66 mhz ts data in set up time 3 ns th data in hold time 2 ns td delay between rising edge of clk and each signal delivered by the multi-hdlc c l = 5 pf (vdd = 3.3v 5% temp 0 to 70c) c l = 30 pf c l = 50 pf 3 3 3 10 12 20 ns ns ns signals provided by the multi-hdlc and received from the synchronous dynamic memory mclk is an input. clock provided by an external clock generation input: data from sdram output: signals to sdram ts th 2.0 1.4 0.8 2.0 1.4 0.8 td t
111/130 STLC5466 4 microprocessor timing 4.1 st9 family; mod0 = 1, mod1 = 0, mod2 = 0 figure 4-1: st9 read cycle tx parameter t min t max unit t1 delay ready /chip select (if t3 >t1), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select /data strobe 14 ns t3 delay ready /nas (if t1 >t3), (30 pf) delay when immediate access 0 98 ns ns t4 width nas 20 ns t5 set up time address /nas 9 ns t6 hold time address /nas 9 ns t7 data valid before ready 0 ns t8 data bus at high impedance after data strobe (30 pf) 0 15 ns t9 set up time r/w /nas 15 ns t10 hold time r/w /data strobe 15 ns t11 width nds when immediate access 50 ns t12 delay nds / ncs 5 ns ncs0/1 ndsack1 / ready nas / ale nds / nrd ad0/7 r/w / nwr a0/7 t6 t5 t7 t8 t9 d0/7 t10 t3 t4 t1 t11 t2 t12
STLC5466 112/130 figure 4-2: st9 write cycle tx parameter t min t max unit t1 delay ready /chip select (if t3 >t1), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select /data strobe 14 ns t3 delay ready /nas (if t1 >t3), (30 pf) delay when immediate access 0 98 ns ns t4 width nas 20 ns t5 set up time address /nas 9 ns t6 hold time address /nas 9 ns t7 set up time data /data strobe -15 ns t8 hold time data /data strobe 15 ns t9 set up time r/w /nas 15 ns t10 hold time r/w /data strobe 15 ns t11 width nds when immediate access 50 ns t12 delay nds / ncs 5 ns a0/7 d0/7 t7 ncs0/1 ndsack1/ ready nas/ ale nds/ nrd ad0/7 r/w / nwr t3 t4 t2 t6 t5 t8 t10 t9 t1 t11 t12
113/130 STLC5466 4.2 st10/c16x mult. a/d; mod0 = 1, mod1 = 0, mod2 = 1 figure 4-3: st10 (c16x) read cycle; multiplexed a/d tx parameter t min t max unit t1 delay not ready /nrd (if ncs0/1=0), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nrd 10 ns t3 delay not ready / nrd rising edge delay when immediate access 0 98 ns ns t4 width ale 20 ns t5 set up time address /ale 5 ns t6 hold time address /ale 5 ns t7 data valid before ready 0 ns t8 data bus at high impedance after nrd (30 pf) 0 15 ns t9 set up time nbhe, addressa16/23 /ale 5 ns t10 hold time nbhe / nrd 10 ns t12 delay nrd / ncs 0 ns ncs0/1 ndsack0 / ndtack / nready nas / ale nds / nrd ad0/15 r/w / nwr nbhe a16/23 a0/15 d0/15 t3 t2 t1 t4 t6 t5 t7 t8 t9 t12 t10
STLC5466 114/130 figure 4-4: st10 (c16x) write cycle; multiplexed a/d tx parameter t min t max unit t1 delay not ready /ale (if ncs0/1=0), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nwr 10 ns t3 delay not ready / nwr rising edge delay when immediate access 0 98 ns ns t4 width ale 20 ns t5 set up time address /ale 5 ns t6 hold time address /ale 5 ns t7 set up time data /nwr -15 ns t8 hold time data /nwr 15 ns t9 set up time nbhe-addressa16/23 /ale 5 ns t10 hold time nbhe-/nwr 10 ns t12 delay nwr / ncs 0 ns ncs0/1 ndsack0/ ndtack / nready nas / ale nds / nrd ad0/15 r/w / nwr nbhe a16/23 a0/15 d0/15 t2 t4 t7 t6 t5 t8 t12 t9 t10 t3 t1
115/130 STLC5466 4.3 st10/c16x demult. a/d; mod0 = 0, mod1 = 1, mod2 = 1 figure 4-5: st10 (c16x) read cycle; demultiplexed a/d tx parameter t min t max unit t1 delay not ready / nrd (if ncs0/1=0), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nrd 10 ns t3 delay not ready / nrd rising edge delay when immediate access 0 98 ns ns t4 width ale 20 ns t7 data valid before notready falling edge (30 pf) 0 ns t8 data bus at high impedance after nrd (30 pf) 0 15 ns t9 set up time nbhe, address ad0/15, a16/ /ale 5 ns t10 hold time nbhe, address ad0/15, a16/23 / nrd 10 ns t12 delay nrd / ncs 0 ns ncs0/1 ndsack0 / dtack / nready nas / ale nds / nrd d0/15 r/w / nwr a0/15 / ad0/15 a16/23 nbhe t3 t2 t1 t4 t7 t8 t9 t12 t10
STLC5466 116/130 figure 4-6: st10 (c16x) write cycle; demultiplexed a/d tx parameter t min t max unit t1 delay not ready / nwr (if ncs0/1=0), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nwr 10 ns t3 delay not ready / nwr rising edge delay when immediate access 0 98 ns ns t4 width ale 20 ns t7 set up time data /nwr -15 ns t8 hold time data /nwr 15 ns t9 set up time nbhe, address ad0/15, a16/23 /ale 5 ns t10 hold time nbhe, address ad0/15, a16/23 /nwr 10 ns t12 delay nwr / ncs 0 ns tx parameter t min t max unit t1 delay not ready / nwr (if ncs0/1=0), (30 pf) delay when immediate access 030ns ncs0/1 ndsack0/ dtack// nready nas / ale nds / nrd d0/15 r/w / nwr a0/15 / ad0/15 a16/23 nbhe t2 t4 t7 t8 t12 t9 t10 t3 t1
117/130 STLC5466 4.4 80c188; mod0 = 1, mod1 = 1, mod2 = 0 figure 4-7: 80c188 read cycle tx parameter t min t max unit t1 delay ready /chip select (if t3 >t1), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nrd 10 ns t3 delay ready /ale (if t1 >t3), (30 pf) delay when immediate access 0 98 ns ns t4 width ale 20 ns t5 set up time address /ale 5 ns t6 hold time address /ale 5 ns t7 data valid before ready 0 ns t8 data bus at high impedance after nrd (30 pf) 0 ns t12 delay nds / ncs 0 ns ncs0/1 ndsack1/ ready nas / ale nds / nrd ad0/7 r/w / nwr a0/7 d0/7 t2 t3 t4 t6 t5 t7 t8 t1 t12
STLC5466 118/130 figure 4-8: 80c188 write cycle tx parameter t min t max unit t1 delay ready /chip select (if t3 >t1), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nwr 10 ns t3 delay ready /ale (if t1 >t3), (30 pf) delay when immediate access 0 98 ns ns t4 width ale 20 ns t5 set up time address /ale 5 ns t6 hold time address /ale 5 ns t7 set up time data /nwr -15 ns t8 hold time data /nwr 15 ns t12 delay nwr / ncs 0 ns ncs0/1 ndsack1/ ready nas / ale nds / nrd ad0/7 r/w / nwr a0/7 d0/7 t2 t3 t4 t7 t6 t5 t8 t1 t12
119/130 STLC5466 4.5 80c186; mod0 = 1, mod1 = 1, mod2 = 1 figure 4-9: 80c186 read cycle tx parameter t min t max unit t1 delay ready /chip select (if t3 >t1), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nrd 10 ns t3 delay ready /ale (if t1 >t3), (30 pf) delay when immediate access 0 98 ns ns t4 width ale 20 ns t5 set up time address /ale 5 ns t6 hold time address /ale 5 ns t7 data valid before ready 0 15 ns t8 data bus at high impedance after nrd (30 pf) 0 ns t9 set up time nbhe-addressa16/19 /ale 5 ns t10 hold time addressa1619 /nrd 10 ns t11 hold time nbhe- /nrd 10 ns t12 delay nrd / ncs 0 ns ncs0/1 ndsack1 / ready nas / ale nds / nrd ad0/15 r/w / nwr nbhe a16/19 a0/15 d0/15 t1 t2 t3 t4 t6 t5 t7 t8 t10 t9 t12 a16/19 nbhe t11 nbhe
STLC5466 120/130 figure 4-10: 80c186 write cycle tx parameter t min t max unit t1 delay ready /chip select (if t3 >t1), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nwr 10 ns t3 delay ready /ale (if t1 >t3), (30 pf) delay when immediate access 0 98 ns ns t4 width ale 20 ns t5 set up time address /ale 5 ns t6 hold time address /ale 5 ns t7 set up time data /nwr -15 ns t8 hold time data /nwr 15 ns t9 set up time nbhe-addressa16/19 /ale 5 ns t10 hold time address16/19/ale 10 ns t11 hold time nbhe-/nwr 10 ns t12 delay nwr / ncs 0 ns ncs0/1 ndsack1/ ready nas / ale nds / nrd ad0/15 r/w / nwr nbhe a16/19 a0/15 d0/15 t1 t2 t3 t4 t7 t6 t5 t8 t12 t10 t9 a16/19 nbhe t11 nbhe
121/130 STLC5466 4.6 386ex: mod0 = 0, mod1 = 1, mod2 = 0 figure 4-11: 386ex read cycle (lba# at vdd) tx parameter min max unit ts set up time/mclk rising edge for clkout, ale, addresses, wrnrd, ncs0/2 6ns th hold time / mclk rising edge for clkout, wrnrd, ncs0/1/2 2 ns tdd data out delay time / mclk rising edge (50 pf) - 20 ns tdh data out hold time / mclk rising edge (50 pf) 4 ns tdz data floating delay / mclk rising edge 4 15 ns ty delay nrdy low / mclk rising edge (50 pf) 4 20 ns tyz nrdy delay floating / mclk rising edge (50 pf) 4 10 ns mclk nds/nrd/ clkout nas/ ale a1/23 a0/ nble size1/ nbhe /nuds 1) no wait state case r/w /nwr/ wrnrd ncs0/1/2 dout 0/15 ndsack0/ ndtack/ nrdy 2) wait state case r/w /nwr/ wrnrd ncs0/1/2 dout 0/15 ndsack0/ ndtack/ nrdy cycle 1 cycle 2 ts th ts th ts th tdd ty ts ts th tdh tdz tyz n twait td1 tdh tdz ty tyz
STLC5466 122/130 figure 4-12: 386ex write cycle (lba# at vdd) lba#, ready# signals delivered by ex386 and nrdy deliverd by the mhdlc tx parameter min max unit ts set up time/mclk rising edge for clkout, ale, addresses, wrnrd, ncs0/2 6ns th hold time / mclk rising edge for clkout, wrnrd, ncs0/1/2 2 ns tdd data out delay time / mclk rising edge (50 pf) - 20 ns tdh data out hold time / mclk rising edge (50 pf) 4 ns tdz data floating delay / mclk rising edge 4 15 ns ty delay nrdy low / mclk rising edge (50 pf) 4 20 ns tyz nrdy delay floating / mclk rising edge (50 pf) 4 10 ns mclk nds/nrd/ clkout nas/ ale a1/23 a0/ nble size1/ nbhe /nuds 1) no wait state case r/w /nwr/ wrnrd ncs0/1/2 din 0/15 ndsack0/ ndtack/ nrdy 2) wait state case ncs0/1/2 din0/15 ndsack0/ ndtack/ nrdy cycle 1 cycle 2 ts th ts th ts th tds ty ts ts th tdh tyz n twait ty tyz th ts stable tds tdh stable ex386 ready# lba# mhdlc nrdy (pin 59) nlba (pin 57) r
123/130 STLC5466 figure 4-13: 386ex; nrdy versus lba# tx parameter min max unit ts set up time/mclk rising edge for clkout, nlba 6 ns th hold time / mclk rising edge for clkout 2 ns ty delay nrdy low / mclk rising edge (50 pf) 4 20 ns tyz nrdy delay floating / mclk rising edge (50 pf) 4 10 ns mclk clkout nlba nrdy delivered by mhdlc ready# delivered by ex 386 nrdy+ready# seen on the bus cycle2 cycle 1 ts th ts ty tyz cycle2 cycle2 or idle cycle 1 cycle 2 3v z 0v 3v z 0v 3v z 0v one twait min or idle or idle
STLC5466 124/130 4.7 68000; mod0 = 0, mod1 = 0, mod2 = 1 figure 4-14: 68000 read cycle tx parameter t min t max unit t1 delay ndtack /ncs0/1 (if t3>t1), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nlds-nuds 0 ns t3 delay ndtack /nlds-nuds falling edge (if t1>t3), (30 pf) delay when immediate access 0 98 ns t4 delay ndtack /nlds-nuds rising edge 0 20 ns t5 set up time address and r/w / last nlds-nuds or ncs 0 ns t6 hold time address and r/w / nlds-nuds 0 ns t7 data valid before ndtack falling edge (30 pf) 0 15 ns t8 data bus at high impedance after nlds-nuds rising edge (30 pf) 015ns t7 t5 t6 t8 t3 t1 t2 t4 ncs0/1 ndtack nas/ ale size0 /nlds size1 /nuds a1/23 r/w / nwr d0/15 a1/23
125/130 STLC5466 figure 4-15: 68000 write cycle tx parameter t min t max unit t1 delay ndtack /ncs0/1 (if t3>t1), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nlds-nuds 0 ns t3 delay ndtack /nlds-nuds falling edge (if t1>t3), (30 pf) delay when immediate access 0 98 ns ns t4 delay ndtack /nlds-nuds rising edge 20 ns t5 set up time address and r/w/last nlds-nuds or ncs 0 ns t6 hold time address /nlds-nuds 0 ns t9 set up time data /nlds-nuds 0 ns t10 hold time data /nlds-nuds 7 ns t6 t3 t1 t2 t4 ncs0/1 ndtack nas/ ale size0 /nlds size1 /nuds a1/23 r/w / nwr d0/15 a1/23 t9 t10 t5
STLC5466 126/130 4.8 68020; mod0 = 0, mod1 = 0, mod2 = 2 figure 4-16: 68020 read cycle tx parameter t min t max unit t1 delay ndsack /ncs0/1 (if t3>t1), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nds rising edge 0 ns t3 delay ndsack1 /nds falling edge (if t1>t3), (30 pf) delay when immediate access 0 98 ns ns t4 delay ndsack1 /nds rising edge 20 ns t5 set up time address and r/w/last nds or ncs 0 ns t6 hold time address /nds 0 ns t7 data valid before ndsack1falling edge (30 pf) 0 15 ns t8 data high impedance after nds (30 pf) 0 15 ns ncs0/1 ndsack0/ ndtack ndsack1/ ready nas / ale nds /nrd size0/ nlds size1/ nuds a 0/23 r/w / nwr d0/15 t1 t2 t5 t6 t4 t7 t3 t8
127/130 STLC5466 figure 4-17: 68020 write cycle tx parameter t min t max unit t1 delay ndtack /ncs0/1 (if t3>t1), (30 pf) delay when immediate access 0 98 ns ns t2 hold time chip select / nds rising edge 0 ns t3 delay ndsack1 /nds falling edge (if t1>t3), (30 pf) delay when immediate access 0 98 ns ns t4 delay ndsack1 /nds rising edge 20 ns t5 set up time address and r/w/last nds or ncs 0 ns t6 hold time address /nds 0 ns t9 set up time data /nds 0 ns t10 hold time data /nds 7 ns ncs0/1 ndsack0/ ndtack ndsack1/ ready nas / ale nds /nrd size0/ nlds size1/ nuds a 0/23 r/w / nwr d0/15 t1 t2 t5 t6 t4 t9 t10 t3
STLC5466 128/130 5 masterclock and token ring timing 5.1 masterclock timing figure 5-1: masterclock tx parameter t min t typ t max unit f masterclock frequency 30 32.768 33.3 mhz th masterclock high 12 ns tl masterclock low 12 ns tx parameter t min t typ t max unit f masterclock frequency 60 65.536 66.6 mhz th masterclock high 6 ns tl masterclock low 6 ns tx parameter t min t typ t max unit f masterclock frequency 45 49.152 50+100p pm mhz th masterclock high 8 ns tl masterclock low 8 ns 1/f masterclock applied to mclk (pin4) th tl
129/130 STLC5466 5.2 token ring timing figure 5-2: token ring tx parameter t min t max unit f f: masterclock frequency 32 66 mhz a delay between masterclock rising edge and edges of tro pulse delivered by the mhdlc (30 pf) 12 ns ts/th this input is sampled in asynchronous mode 5 ns a ts th 1/f a masterclock applied to mclk pin tro tri
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